Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET (PART-3)

By Chandani Prakash|Updated : April 20th, 2021

In this article, you will find the Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET which will cover the topics such as Basics of MOSFET, Drain Current equation for Triode and Saturation Region, Operating Condition of MOSFET, MOS Transconductance, Different biasing methods of MOSFET

In this article, you will find the Circuits Analysis and Applications of Diodes, BJT, FET and MOSFET which will cover the topics such as Basics of MOSFET, Drain Current equation for Triode and Saturation Region, Operating Condition of MOSFET, MOS Transconductance, Different biasing methods of MOSFET

1.Basics of Mosfet:

A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a field effect transistor (FET with an insulated gate) where the voltage determines the conductivity of the device. It is used for switching or amplifying signals. The ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. MOSFETs are now even more common than BJTs in digital and analog circuits.

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Figure 1: Basic MOSFET structure

There are three possible regions for the working of the MOSFET.

  1. Triode Region
  2. Cut-off Region
  3. Saturation Region

2.Drain Current Equation:

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Where μn = mobility of electron

Cox = Capacitance of oxide layer

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   VDS = drain to source voltage

2.1    Triode region

VDS < VGS – Vt    , if VDS (mV)

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2.2    Current Saturation

VDS ≥ VGS – Vt

(VDS)Sat = VGS – Vt

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→ gm should be more, so kn should be more μn → faster, gain → higher.

→ A good MOSFET should have high value of kn

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3.Operating Condition for MOSFET:

3.1.Operating Condition for N channel Enhancement type MOSFET:

 

Operating region

Required condition

Cut off region

VGS < VTN

Triode region

VGS > VTN, VDS < VDS(sat) (or) VDS < VGS – VTN

Saturation region

VGS > VTN, VDS > VDS(sat) (or) VDS  > VGS –VTN

3.2.Operating Condition for P channel Enhancement type MOSFET:

 

Operating region

Required condition

Cut off region

VSG < |VTP|

Triode region

VSG > |VTP|, VSD < VSD(sat) or VSD < VSG + VTP

Saturation region

VSG > |VTP|, VSD > VSD (sat) or VSD > VSG + VTP

3.3.Operating Condition for N channel depletion type MOSFET:

 

Operating region

Required condition

Cut off region

VGS < VTN

Triode region

VGS > VTN, VDS < VDS(sat) (or) VDS < VGS – VTN

Saturation region

VGS > VTN, VDS > VDS(sat) (or) VDS > VGS – VTN

3.4.Operating Condition for P channel depletion type MOSFET:

 

Operating region

Required condition

Cutoff region

VSG < VTP

Triode region

VSG > VTP, VSD < VSD(sat) (or) VSD < VSG + VTP

Saturation region

VSG > |VTP|, VSD > VSD(sat) (or) VSG + VTP

  1. MOS Transconductance:

As a voltage-controlled source, a MOS transistor can be characterized by its transconductance

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Various dependencies of gm

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5.Different biasing methods of MOSFET:

There are four biasing methods for MOSFET: -

  1. Drain to gate bias
  2. Voltage divider bias
  3. Fixed bias
  4. Self bias

5.1.Drain to gate bias configuration: -

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Drain to gate bias Configuration

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                DC Equivalent

DC Analysis-                  

Gate current , IG =0

So, we have voltage drop across resistance RG = VRG = 0

Therefore, we get a direct connection between drain and source i.e.

VD = VG

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Note:

Drain to gate bias always enables MOSFET in saturation region

For output circuit, we have

VDS = VDD – IDRD

 

5.2. Voltage divider bias configuration:

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Voltage Divider Configuration

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DC Equivalent

DC – ANALYSIS:

Using voltage divider, gate voltage is obtained by:

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Applying KVL is loop 1, we get

VG – VGS – IDRS = 0

VGS = VG – IDRS …. (1)

Assume that MOSFET is in saturation, so we have ID = Kn (VGS – VTN)2

By solving the quadratic equation, determine the value of VGS or ID, then apply KVL in source to drain loop

VDD – IDRD – VDS – ISRS = 0

VDS = VDD – ID (RS + RD)

If VDS > VGS – VTN, then the transistor is indeed biased in saturation region, as we have assumed.

However, if VDS < VDS (sat), then transistor is biased in the non saturation region

Therefore from equation (1)

VGS = VG – IDRS

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5.3.Fixed bias configuration:

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Fixed bias Configuration

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DC Equivalent

(In DC model, RG is short and input impedance is very high i.e. (IG ≃ 0))

 DRAWBACK OF FIXED BIAS:

It is a dual battery design which makes it expensive and more space occupied bias Configuration.

5.4.Self bias configuration:

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Self Bias Configuration

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DC Equivalent

DC ANALYSIS:

0 = VGS + IDRS

VGS = – IDRS

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