JK Flip-Flop Excitation Table

By Priyanshu Vaish|Updated : May 9th, 2022

JK Flip-Flop: The JK Flip-Flop is one of the most used flip flops in digital circuits. The JK Flip-Flop is the universal flip flop having two inputs, 'J' and 'K'. The JK Flip-Flop is a gated SR Flip-Flop with a clock input circuitry that prevents the illegal or invalid output state that can arise when both inputs S and R are equal to logic level "1."

In the SR Flip-Flop, the 'S' and 'R' are the shortened abbreviated letters for the Set and Reset, but J and K are not. Instead, the J and K are autonomous letters chosen to distinguish the flip flop design from other types. Let us discuss in detail about JK Flip-Flop in the upcoming sections.

Table of Content

What is JK Flip-Flop?

The JK Flip-Flop is a refinement of the S-R flipflop in which the indeterminate (invalid) state of the S-R type is defined. The logic diagram of JK Flip-Flop with data input J and K ANDed with O and Q respectively to obtain S and R inputs that is

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JK Flip-Flop Truth Table

The truth table of the JK Flip-Flop has the hold state, reset state, set state, and toggle state. The truth table is given below.

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Characteristic Table of JK Flip-Flop

The characteristic table of the JK Flip-Flop has the hold state, reset state, set state, and toggle state. The characteristic table is given below.

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JK Flip-Flop Characteristic Equation

The characteristic equation of the JK Flip-Flop that has the hold state, reset state, set state, and toggle state that is as follows using the three variable k-map:  

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Excitation Table of JK Flip-Flop

The excitation table of the JK Flip-Flop that has the Qn and Qn+1 as previous and next sate, respectively, are as follows:  

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Case-A: When, Qn = 0 and Qn+ 1 = 0

This condition can happen with either J = 0 and K = 0 or J = 0 and K = 1 (Characteristic table)

Therefore, the desired output Qn+1 = 0 is obtained when J= 0 and K= X (don’t care).

Case-B: When, Qn = 0 and Qn+ 1 = 1

This can happen with either J = 1 and K = 0 or J= 1 and K= 1 (toggle condition)

Therefore the desired output Qn+ 1 = 1 is obtained when J= 1 and K=X (don’t care).

Case-C: When, Qn = 1 and Qn+ 1 = 0

This can happen with either J=0 and K= 1 or J= 1 and K=1.

Therefore, the desired output Qn+ 1  = 0 is obtained when J= X (don’t care) and K=1.

Case-D: When, Qn = 1 and Qn+ 1  = 1

This condition can happen with either J= 0 and K= 0 or J= 1 and K=0.

Thus, the desired output Qn+ 1  = 1 is obtained with J = X and K=0. 

Race Around Condition

The difficulty of both the inputs to be '1' in the case of S-R of the invalid state is eliminated by a JK Flip-Flop using feedback connections from output to the input, as shown below. However, the condition when (level triggered) J = K = 1 is not yet perfect,

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Consider J = K = 1 and Qn = 0 and a clock (CLK) is applied. After a propagation delay time tpd through two NAND gates, the output will toggle to Qn = 1. Since this is feedback to the inputs, the output will toggle back to Qn = 0 after another delay of tpd (FF).

Thus, as long as the clock pulse is present (tow), the output will toggle at every tpd(FF), and at the end of the clock pulse, the value of Qn is uncertain. This situation will continue as long as the low clock pulse width is longer than the flipflop propagation delay (tpd). Such a situation is referred to as the "race around condition".
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Thus, the "Race around condition" will occur when
(i) J= K = 1
(ii) When tpd (FF) < tpw
(iii) When the level trigger is applied.
One way to avoid this problem is to maintain tpw < Tpd(FF) < T. A most practical method for overcoming this problem is the use of the "Master-slave configuration".

Master-Slave Flip-Flop

A "M-S FF" is constructed from 2 FFs (a MASTER and a SLAVE) and an 'INVERTER'.

  • On the rising edge of CLK (that is, +ve edge CLK PULSE), the control inputs are used to determine the output of the "MASTER". When the CLK goes LOW (i.e. -ve edge CLK PULSE), the state of Master is transferred to the "SLAVE", whose outputs are Q and Q'
  • In the "M-S FF", the output is fully dependent upon the output of SLAVE-FF.

Logic Diagram of M-S FF

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Operation

  • When the clock pulse CLK is 0, the output of the inverter is 1. Since the clock input of the slave is 1, the flipflop is enabled, and output Q is equal to Y, while õ is equal to 7. The master flipflop is disabled because CLK = 0.
  • When the pulse becomes 1, the information at the external R and S inputs is transmitted to the master Flip-Flop. In the slave flipflop, the clock is zero because the inverter output is zero. That is a slave flipflop is isolated
  • When the pulse returns to the master flip-flop is isolated, preventing external inputs from affecting it. The slave flip-flop then goes to the same state as the master flip-flop.

Timing diagram in M-S FF 

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Master Salve JK Flip-Flop by using only NAND gates

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FAQs

  • The JK Flip-Flop is the gated SR flipflop with the addition of a clock input circuitry that prevents the invalid or illegal output condition that can occur when both the inputs S and R are equal to logic one.

  • JK Flip-Flop is the universal flipflop that makes the circuit toggle between two states and is widely used in shift registers, counters, PWM and computer applications.

  • If inputs J and K have high inputs assigned to them, the output Q toggles between the high and two states. As a result, there are no ambiguous states, and the JK Flip-Flop can operate as a set/reset flip-flop.

  • The fullform of JK Flip-Flop Jack Kilby. The JK Flip-Flop is a gated SR flip-flop with the addition of a clock input circuitry that prevents the illegal or invalid output condition that can occur when both inputs S and R are equal to logic level "1".

  • JK Flip-Flop has a drawback of timing problem known as "RACE". The condition of RACE arises if the output Q changes its state before the timing pulse of the clock input has time to go in the OFF state. Therefore, the timing pulse period (T) should be kept as short as possible to avoid the problem of timing.

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