Combinational Circuits -2 Study Notes for GATE & Computer Science Engineering Exams

Arithmetic Circuits

Arithmetic circuits are usually used to perform addition and subtraction. Binary adder and binary subtractor performs binary addition and binary subtraction respectively .

Classification of Adder are – (i) Half Adder  (ii) Full Adder

Classification of Subtractor are – (i) Half Subtractor and (ii) Full Subtractor

Half Adder: This circuit is used for the addition of two one-bit numbers.

• The truth table of Half Adder:

• Half adder circuit:

Sum (S) =

Carry (C) = AB

• Implement of Half Adder Using NAND Gate:

Note: Required number of NAND Gates to implement Half Adder = 5

• Implement of Half Adder Using NOR Gate:

Note: Required number of NOR Gates to implement Half Adder = 5

Full Adder

This is combinational logic circuit that performs the arithmetic sum of three input bits. It consists of three inputs and two outputs.

Truth table for Full Adder:

Logic diagram of Full Adder:

• Sum (S) =
• Carry (C₀) = AB + BC + AC

• A full adder = 2 Half adder + 1 OR Gate
• Required minimum number of NAND gate to implement FA = 9
• Required minimum number of NOR gate to implement FA = 9

Half Subtractor

It is a combinational logic circuit that subtracts two bit and produces their difference and borrow.

Logic Diagram- Half Subtractor:

• Difference (D)
• Borrow (B₀) =
• To implement half subtractor the total number of NAND/NOR are required = 5

Full Subtractor

It is a combinational logic circuit that performs subtraction involving three bit naming minuid bit, subtrahend bit and borrow from the previous stage

• Difference (D)
• 
• A full subtractor = 2 half subtractor + 1 OR gate
• To implement full subtractor of NAND/NOR gates are required = 9

Multiplexer (MUX)

• It is a combinational circuit that selects binary information from one of the many input lines and directs it to a single output line.
• The selection of a particular input line is controlled by a set of selection lines.
• MUX is also called: Many to one, Data selector, Universal circuit, or Parallel data serial.
• Multiplexing means transmitting a large number of information units over a smaller number of channels or lines. It is abbreviated as MUX.
• There are 2ⁿ input lines and n selection lines whose bit combinations determine which input is selected.

m = 2ⁿ implies n = log m where m = Number of data inputs, and n = Number of select lines.

2 × 1 MUX :

Universal equation

Implementation of one MUX using another MUX:

Demultiplexer (DEMUX)

• It is a circuit that receives information on a single line and transmits this information on one of 2ⁿ possible output lines.
• The selection of a specific output line is controlled by the bit values of n selected lines.

1 × 2 Demux:

D₀ = S′I

D₁ = SI

• Truth table of 1 × 2 Demux:

• Circuit Diagram of 1 × 2 Demux:

• 1 × 4 Demux:
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  • 
  • 
  • 

• Truth table of 1 × 4 Demux:

• Circuit Diagram of 1 × 4 Demux:

• DEMUX Implementation using another DEMUX:

Decoders

• A decoder is a combinational circuit that converts binary information from n input lines to a maximum 2ⁿ unique output lines.
• If the n-bit decoded information has unused or don’t-care combinations, the decoder output will have fewer than 2ⁿ outputs.
• The decoders presented here are n-to-m-line decoders, where m ≤ 2ⁿ. Their purpose is to generate the 2ⁿ (or fewer) minterms of n input variables.

2 × 4 Decoder:

• 
• 
• 
• 

Tutht table of 2 × 4 Decoder:

Encoders

• It is a combinational circuit that converts information into coded form (binary).
• It is a digital circuit that performs the inverse operation of a decoder.
• An encoder has 2ⁿ (or fewer) input lines and n output lines.
• The output lines generate the binary code corresponding to the input value.

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