VLSI design Study Notes for EC

INSTRUCTION PIPELINE

Pipelining is a technique where multiple instructions are overlapped during execution. The pipeline is divided into stages and these stages are connected with one another to form a pipe-like structure. Instructions enter from one end and exit from another end.

Pipelining increases the overall instruction throughput.
An instruction in a process is divided into 5 subtasks:

Instruction Fetch

Instruction Decode

Operand Fetch

Instruction Execute

Operand Store

Pipeline Stages

RISC processor has 5 stage instruction pipelines to execute all the instructions in the RISC instruction set. Following are the 5 stages of RISC pipeline with their respective operations:

Stage 1 (Instruction Fetch)

In this stage the CPU reads instructions from the address in the memory whose value is present in the program counter.

Stage 2 (Instruction Decode)

In this stage, instruction is decoded and the register file is accessed to get the values from the registers used in the instruction.

Stage 3 (Instruction Execute)

In this stage, ALU operations are performed.

Stage 4 (Memory Access)

In this stage, memory operands are read and written from/to the memory that is present in the instruction.

Stage 5 (Write Back)

In this stage, computed/fetched value is written back to the register present in the instructions.

Each step is executed in a particular segment, and there are times when different segments may take different times to operate on the incoming information. Moreover, there are times when two or more segments may require memory access at the same time, causing one segment to wait until another is finished with the memory.
Advantages of Pipelining
The cycle time of the processor is reduced.
It increases the throughput of the system.
It makes the system reliable.
Disadvantages of Pipelining
The design of pipelined processor is complex and costly to manufacture.
The instruction latency is more.

Pipelined vs Non-Pipelined:

Pipelined	Non-Pipelined
Pipelined microprocessor bus cycle is an implementation technique where multiple instructions are overlapped in execution and has high throughput (amount of instructions executed per unit time).	Non- pipeline microprocessor bus cycle is all the actions, (decoding, encoding, executing of instructions, and writing the results on the memory) are grouped into a single step.
The pipeline is filled by the CPU scheduler from a pool from a piece of work that is waiting to occur, and each execution unit has a pipeline attached to it so as to have work pre planned.	The CPU scheduler in the case of non-pipeline merely chooses from the pool of waiting for work when the execution unit gives a single that is free.
If the workload is such that the scheduler can't do a good job, frequent pipeline stalls occur.	It is not dependent on the scheduler.
It has a high throughput.	It has a low throughput.

Hazards:

Hazards are also called delays.
It prevents the next instruction in the instruction stream from being executing during its designated clock cycle.
Hazards reduce the performance from the ideal speedup gained by pipelining.
There are three type of hazards:
Structural Hazards:

It occurs due to resource conflict in the pipeline i.e. when two instructions need the same hardware resource at the same time.
The result is that instruction must be executed in series rather than parallel for a portion of pipeline.
Structural hazards are sometime referred to as resource hazards.
For example, a situation in which multiple instructions are ready to enter the execute instruction phase and there is a single ALU. If processor has only one register file write port and two instructions want to write in the register file at the same time.
Data Hazards:

RAW (Read after Write) [Flow/True data dependency]
WAR (Write after Read) [Anti-Data dependency]
WAW (Write after Write) [Output data dependency]

Let there be two instructions I and J, such that J follow I. Then,

RAW hazard occurs when instruction J tries to read data before instruction, I writes it.
Eg:
I: R2 <- R1 + R3

J: R4 <- R2 + R3

WAR hazard occurs when instruction J tries to write data before instruction, I reads it.

Eg:
I: R2 <- R1 + R3

J: R3 <- R4 + R5

iii. WAW hazard occurs when instruction J tries to write output before instruction, I writes it.
Eg:
I: R2 <- R1 + R3

J: R2 <- R4 + R5

WAR and WAW hazards occur during the out-of-order execution of the instructions.

Control Hazards:

Control hazards arise from branch, jump, and other transfer of control instructions are executed.
Due to execution of control hazards, unwanted instructions are executed in the pipeline, so it brings unwanted behaviour in the program output.

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