Electronic Devices and Circuits : Device Technology

By V V Satya Narayana Madasu|Updated : July 7th, 2021

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In this article, you will find the Study Notes on Integrated Circuit Fabrication Process which will cover the topics such as Introduction, Fabrication Steps, Fabrication Process and Twin Tub CMOS Process.

1. Introduction

  • Integrated circuits compose the major portion of the field of microelectronics and may consist of film, monolithic or hybrid circuits.
  • A monolithic IC consists of active and passive components formed by diffusion into a single silicon chip, with interconnection provided by an aluminium metallization process.
  • Silicon is a semiconductor with resistance between that of conductor and an insulator.
  • The conductivity of silicon can be changed several orders of magnitude by introducing impurity atoms in silicon crystal lattice.

2. Fabrication Steps

The monolithic fabrication process consists of wafer preparation, epitaxial growth, diffused isolation, base and emitter diffusions, pre-ohmic etch, metallization, circuit probing, dicing, mounting and packaging, wire bonding, encapsulation and final testing.

  • Each diffusion process involves such as items silicon dioxide layer, photo resist mask, ultraviolet exposure, etching, scrubbing and diffusion.
  • Practical IC resistance values obtainable range from 25 Ω to 500 k Ω, depending upon the sheet resistivities measured in ohms per square. p-type diffused resistors have values from 50 to 250 Ω per square and pinch resistors have a value of 5000 Q per square.
  • Because the tolerances of resistance values are at best ±30%, ICs are designed to utilize resistance ratios, which may be controlled to within 3%.
  • Capacitors may be obtained by utilising the p-n junctions in transistor type structures or the MOS capacitive effects employing the silicon-dioxide layer. Practical values range from 3 to 30 pF because of the excessive area used for larger values.
  • By suitable interconnecting COS/MOS ICs, an inverter circuit with very low quiescent dissipation can be made available, and by further interconnections of many inverters, many of the logic gates found in digital systems may be implemented.
  • Integrated circuits may be of the monolithic or hybrid type, with the latter being a mixture of thin-film and diffused components.
  • Complementary Symmetry MOS ICs (COS/MOS) involves both a p-channel and an n-channel MOSFET fabricated on the same chip.
  • Large Scale Integration (LSI) involves the fabrication of 100 or more logic gates on a single chip, while Medium Scale Integration (MSI) is defined as more than 12 but less than 100 gates on a single chip.

3. Fabrication Process

The fabrication of integrated circuits consists basically of the following process steps:

  • Lithography: The process for pattern definition by applying a thin uniform layer of viscous liquid (photo-resist) on the wafer surface. The photoresist is hardened by baking and then selectively removed by the projection of light through a reticle containing mask information.
  • Etching: Selectively removing unwanted material from the surface of the wafer. The pattern of the photoresist is transferred to the wafer by means of etching agents.
  • Deposition: Films of the various materials are applied on the wafer. For this purpose mostly two kinds of processes are used, physical vapour deposition (PVD) and chemical vapour deposition (CVD).
  • Chemical Mechanical Polishing: A planarization technique by applying chemical slurry with etchant agents to the wafer surface.
  • Oxidation: In the oxidation process oxygen (dry oxidation) or H2O (wet oxidation) molecules convert silicon layers on top of the wafer to silicon dioxide.
  • Ion Implantation: Most widely used technique to introduce dopant impurities into the semiconductor. The ionized particles are accelerated through an electrical field and targeted at the semiconductor wafer.
  • Diffusion: A diffusion step following ion implantation is used to anneal bombardment-induced lattice defects.


  • It is a process which converts silicon on the wafer into silicon dioxide.
  • The chemical reaction of silicon and oxygen already starts at room temperature but stops after a very thin native oxide film.
  • For an effective oxidation rate, the wafer must be settled to a furnace with oxygen or water vapour at elevated temperatures.
  • Silicon dioxide layers are used as high-quality insulators or masks for ion implantation.
  • The ability of silicon is to form high-quality silicon dioxide.


  • Diffusion is the movement of impurity atoms in a semiconductor material at high temperatures.
  • The driving force of diffusion is the concentration gradient.
  • There is a wide range of diffusivities for the various dopant species, which depend on how easy the respective dopant impurity can move through the material.
  • Diffusion is applied to anneal the crystal defects after ion implantation or to introduce dopant atoms into silicon from a chemical vapour source.
  • In the last case, the diffusion time and temperature determine the depth of dopant penetration.
  • Diffusion is used to form the source, drain, and channel regions in an MOS transistor.
  • But diffusion can also be an unwanted parasitic effect because it takes place during all high-temperature process steps.

Ion Implantation:

  • Ion Implantation is the process of adding impurities to a silicon wafer.
  • This is performed with an electric field which accelerates the ionized atoms or molecules so that these particles penetrate into the target material until they come to rest because of interactions with the silicon atoms.
  • Ion implantation is able to control exactly the distribution and dose of the dopants in silicon because the penetration depth depends on the kinetic energy of the ions which is proportional to the electric field. The dopant dose can be controlled by varying the ion source.
  • Unfortunately, after ion implantation, the crystal structure is damaged this implies worse electrical properties.
  • Another problem is that the implanted dopants are electrically inactive because they are situated on interstitial sites.
  • Therefore after ion implantation, a thermal process step is necessary which repairs the crystal damage and activates the dopants.


  • Lithography is used to transfer a pattern from a photomask to the surface of the wafer.
  • Photolithography is the process of creating patterns on a smooth surface (Silicon wafer).
  • This is accomplished by selectively exposing parts of the wafer while other parts are protected. The exposed sections are susceptible to doping, removal, or metallization. Specific patterns can be created to form regions of conductors, insulators, or doping. Putting these patterns onto a wafer is called photolithography.
  • The pattern defined by the mask is either removed or remained after development, depending if the type of resist is positive or negative.


  • Etching is used to remove material selectively in order to create patterns.
  • The pattern is defined by the etching mask, because the parts of the material, which should remain, are protected by the mask.
  • The unmasked material can be removed either by wet (chemical) or dry (physical) etching.

4. Twin-tub CMOS process

  • It is also possible to create both a p-well and an n-well for the n-MOSFET's and p-MOSFET respectively in the twin well or twin tub technology. Such a choice means that the process is independent of the dopant type of the starting substrate (provided it is only lightly doped).
  • Provide separate optimization of the n-type and p-type transistors.
  • It is possible for threshold voltage, body effect and the channel transconductance of both types of transistors to be tuned independently.
  • Generally, the starting material is a p+ or n+ substrate, with a lightly doped epitaxial layer on top. This epitaxial layer provides the actual substrate on which the n-well and the p-well are formed.
  • Since two independent doping steps are performed for the creation of the well regions, the dopant concentrations can be carefully optimized to produce the desired device characteristics.
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