1. Bipolar Junction Transistor (BJT)
- A Bipolar Junction Transistor (BJT) has three terminals connected to three doped semiconductor regions.
- In an NPN transistor, a thin and lightly doped P-type base is sandwiched between a heavily doped N-type emitter and another N-type collector
- In a PNP transistor, a thin and lightly doped N-type base is sandwiched between a heavily doped P-type emitter and another P-type collector.
- Terminals of BJT: BJT has three terminals. They are Emitter, Base, and Collector. An emitter is heavily doped, a collector is moderately doped and a base is lightly doped. A transistor is an active device which has the ability to control the electron flow through it.
- The direction of arrow signifies the direction of emitter current when base emitter junction is forward biased.
- An NPN transistor can be considered as two diodes with a shared anode region. In typical operation, the emitter–base junction is forward biased and the base–collector junction is reverse biased.
2. Configurations of BJT
- BJT can be operated in three configurations. They are Common Base, Common Emitter, and Common collector configurations.
- Due to the presence of two junctions each junction can be operated in forward or reverse bias leading to three different regions of operation.
- The transistor as a Switch
- The transistor can be used as a switch in logic gates will be operated in extreme regions of input output characteristics in which both regions will be forward biased (On state) or reverse biased (Off state) which are called saturation and cut off regions of operation simultaneously.
- Transistor as an amplifier
- Transistor, when used as an amplifier, is operated in the active region in which input junction will be forward biased and output junction will be reverse biased. There are three types of operating modes of amplifier i.e. Common Base (CB) amplifier, Common Emitter (CE) amplifier and Common Emitter (CE) amplifier. Another region inverse active region is of less importance in practice.
3. MOS capacitor
- An MOS capacitor is made of a semiconductor body or substrate, an insulator film, such as SiO2, and a metal electrode called a gate.
- A capacitor is formed when two conducting layers are separated by a dielectric layer.
- The value of MOS capacitor depends on the region of operation.
- The flat band voltage is an important term related to the MOS capacitor. It is defined as the voltage at which there is no charge on the capacitor plates and hence there is no static electric field across the oxide.
- Accumulation: An applied positive gate voltage larger than the flat band voltage (VGB > VFB) then a positive charge is induced on the metal (poly silicon) gate and negative charge in the semiconductor. The only negative charged electrons are available as negative charges and they accumulate at the surface. This is known as surface accumulation.
- Depletion: If the applied gate voltage is lower than the flat band voltage (VGB < VFB) then a negative charge is induced at the interface between the polysilicon gate and the oxide and positive charge in the semiconductor. This is only possible by pushing the negatively charged electrons away from the surface exposing the fixed positive charges from donors. This is known as surface depletion.
- Inversion: As the potential across the semiconductor increases beyond twice the bulk potential, another type of negative charge emerges at the oxide-semiconductor interface: this charge is due to minority carriers, which form a so-called inversion layer.
For Detailed Notes on BJT please visit the following Link:
4. Introduction to JFET
- The FET is a three-terminal device like the BJT but operates by a different principle. The three terminals are called the source, drain, and gate. The voltage applied to the gate controls the current flowing in the source-drain channel. No current flows through the gate electrode, thus the gate is essentially insulated from the source-drain channel. Because no current flows through the gate, the input impedance of the FET is extremely large (in the range of 1010–1015 Ω). The large input impedance of the FET makes them an excellent choice for amplifier inputs.
- The two common families of FETs, the junction FET (JFET) and the metal oxide semiconductor FET (MOSFET) differ in the way the gate contact is made on the source-drain channel.
- In the JFET the gate-channel contact is a reverse-biased PN junction. The gate-channel junction of the JFET must always be reverse biased otherwise it may behave as a diode. All JFETs are depletion mode devices—they are on when the gate bias is zero (VGS = 0). In the MOSFET the gate-channel contact is a metal electrode separated from the channel by a thin layer of insulating oxide. MOSFETs have very good isolation between the gate and the channel, but the thin oxide is easily damaged (punctured!) by static discharge through careless handling. MOSFETs are made in both depletion mode (on with zero biased gates, VGS = 0) and in enhancement mode (off with zero biased gates).
- In this class, we will focus on JFETs.
- Schematic symbols:
- Regions of JFET operation:
- Cut-off region: The transistor is off. There is no conduction between the drain and the source when the gate-source voltage is greater than the cut-off voltage. (ID = 0 for VGS > VGS,off)
- The active region (also called the Saturation region): The transistor is on. The drain current is controlled by the gate-source voltage (VGS) and relatively insensitive to VDS. In this region, the transistor can be an amplifier. IDSS is a parameter that is the maximum drain current, which occurs when the VGS = 0. (The drain current with source shorted to the gate.)
- Ohmic region: The transistor is on, but behaves as a voltage-controlled resistor. When VDS is less than in the active region, the drain current is roughly proportional to the source-drain voltage and is controlled by the gate voltage.
5. Common Circuit Applications
- Voltage Controlled Switch. For the on state the gate voltage VGS = 0 and for the off state |VGS| > |VGS, off| (of greater magnitude than VGS, off and with the same sign). The sign of the voltage depends on the type of FET, negative for n-channel and positive for p-channel.
- Current Source. The drain current is set by RS such that VGS = −IDRS. Any value of current can be chosen between zero and IDSS (see the ID vs VGS graph for the JFET).
- Source Follower. The simple source follower is shown below. The improved version is shown at the right. The lower JFET forms a current source. The result is that VGS is held constant, removing the defects of the simple circuit.
- Voltage-Controlled Resistor. VGS must be between zero and VGS, off
- JFET Diode. The JET pn gate junction can be used as a diode by connecting the source and the drain terminals. This is done if very low reverse leakage currents are required. The leakage current is very low because of the reverse leakage current scales with the gate area. Small gate areas are designed into JFETs because it decreases the gate-source and the gate-drain capacitances.
The MOSFET is a four-terminal device with the source(S), gate (G), drain (D) and body (B) terminals. The body of the MOSFET is frequently connected to the source terminal so making it a three-terminal device like field-effect transistor.
- The MOSFET is a field effect transistor in which the metal gate is insulated by a very thin oxide layer from the semiconductor channel. Both depletion and enhancement types of MOSFET are available in the former, drain current may be controlled by either enhancing or depleting the channel that exists between drain and source, but in the enhancement type drain current flows only when a channel is induced by enhancing carrier concentration.
- The MOSFET is a core of integrated circuit and it can be designed and fabricated on a single chip because of these very small sizes.
- The MOSFET can function in two ways: Deflection Mode, and Enhancement Mode.
- Deflection Mode: When there is no voltage on the gate, the channel shows its maximum conductance. As the voltage on the gate is either positive or negative, the channel conductivity decreases.
- Enhancement mode: When there is no voltage on the gate the device does not conduct. More is the voltage on the gate, the better the device can conduct.
n-Channel Enhancement-Type MOSFET (NMOS)
- The physical structure of an n-Channel Enhancement-Type MOSFET (NMOS) is shown. The device is fabricated on a p-type substrate (or Body). Two heavily doped n-type regions (Source and Drain) are created in the substrate. A thin (fraction of a micron) layer of SiO2, which is an excellent electrical insulator, is deposited between a source and drain region. Metal is deposited on the insulator to form the Gate of the device (thus, metal-oxide semiconductor). Metal contacts are also made to the source, drain, and body region.
- Body Effect:
In driving NMOS (and other MOS) iD versus vDS characteristics, we had assumed that the body and source are connected. This is not possible with an integrated chip which has a common body and a large number of MOS devices (connection of body to source for all devices means that all sources are connected). The common practice is to attach the body of the chip to the smallest voltage available from the power supply (zero or negative). In this case, the pn junction between the body and source of all devices will be reversed biased. The impact of this to the lower threshold voltage for the MOS devices slightly and it's called the body effect. Body effect can degrade device performance. For analysis here, we will assume that body effect is negligible.
p-Channel Enhancement-Type MOSFET (PMOS)
- The physical structure of a PMOS is identical to an NMOS except that the semiconductor types are interchanged, i.e., body and gate are made of n-type material and source and drain are made of p-type material and a p-type channel is formed. As the sign of the charge carriers is reversed, all voltages and currents in a PMOS are reversed. By convention, the drain current is flowing out of the drain as is shown. With this, all of the NMOS discussion above applies to PMOS as long as we multiply all voltages by a minus sign:
The depletion-type MOSFET has a structure similar to the enhancement-type MOSFET with only one important difference; depletion-type MOSFET has a physically implanted channel. Thus, an n-type depletion-type MOSFET has already an n-type channel between drain and source. When a voltage vDS is applied to the device, a current ID = IDSS flows even for vGS = 0. (Show IDDS = KVt2 .) Similar to NMOS, if vGS is increased, the channel becomes wider and iD increases. However, in an n-type depletion-type MOSFET, a negative vGS can also be applied to the device, which makes the channel smaller and reduces iD. As such, negative vGS “depletes” the channels from n-type carriers leading to the name depletion-type MOSFET. If vGS is reduced further, at some threshold value Vt (which is negative), the channel disappears and iD = 0, as is seen in the figure. It should be obvious that a depletion-type MOSFET can be operated either in enhancement mode or in depletion mode. p-type depletion MOSFET operate similarly to p-type enhancement MOSFET expect that Vt > 0 for depletion type and Vt < 0 for the enhancement type. The figure below shows iD versus vGS of four types of MOSFET devices in the active region. Circuit symbols for depletion-type MOSFET devices are also shown
You can avail of Online Classroom Program for all AE & JE Exams:
You can avail of BYJU'S Exam Prep Test Series specially designed for all AE & JE Exams:
Team BYJU'S Exam Prep
Sahi Prep Hai to Life Set Hai !!!
Download BYJU'S Exam Prep APP , for best Exam Preparation , Free Mock Test, Live Classes