# Computer Organization & Architecture: Assembly Language Programming

By Mayank Soni|Updated : July 14th, 2021

Dedicated Freight Corridor Corporation of India Limited (DFCCIL) is a Public Sector Undertaking under the administrative control of the Government of India (Ministry of Railways), has given the notification of 1074 Vacancies for recruitment of Junior Executive, Executive, and Junior Manager in Civil, Electrical, S&T, Operations & BD, and Mechanical Departments of DFCCIL. This is a great opportunity for Electronics and Electricals students to work with one of the top PSUs and make their career. As Competition is high, so the aspirants need to prepare with a good strategy and proper planning to clear this exam.

BYJU'S Exam Prep Brings you 60 Days Study Plan for the preparation of DFCCIL Electricals & Electronics Engineering. This Study Plan will be free and will be very beneficial for the students preparing and targeting the DFCCIL Exam. Save this article as it will get updated on a daily basis as scheduled.

Some Example of  Assembly  Language Program

Example-1: Write 8085 assembly program for multiplying two 8 bit numbers.

• MVI A,00 ; Load immediate data into accumulator.
• MVI B,02 ; Load immediate data into register B.
• MVI C,04 ; Load immediate data into register C.
• DCR C ; Decrement the content of register C by 1.
• JNZ LOOP
• STA 1000 H ; Store the content of accumulator to memory location 1000 H
• HLT ; Halt

Example-2: Write 8085 assembly program to find the largest number in an array of data.

• LXI H, 1000 ; Load the address of the first element of the array in HL pair
• MOV B, M ; Load the Count
• INX H ; Set first element as largest data
• MOV A, M ; Get the first data in A
• DCR B ; Decrements the count
• LOOP: INX H
• CMP M ; Compare A and M
• JNC AHEAD ; if no carry (A>M) then go to AHEAD
• MOV A, M ; Set the new value as largest
• JNZ LOOP ; Repeat comparisons till count = 0
• STA 2000 ; Store the largest value at 2000
• HLT

Direct Memory Access: Direct memory access (DMA) facilitates data transfer operations between main memory and I/O subsystems with limited CPU intervention. The majority of I/O devices provide two methods for transferring data between a device and memory.

• Programmed I/O (PIO): It is fairly easy to implement, but requires the processor to constantly read or write a single memory word (8-bits, 16-bits or 32-bits, depending on the device interface) until the data transfer is complete. Although PIO is not necessarily slower than DMA, it does consume more processor cycles and can be detrimental in a multi-processing environment.
• DMA : It allows a system to issue an I/O command to a device, initiate a DMA transaction and then place the process in a waiting queue. The system can now continue by selecting another process for execution, thereby utilizing the CPU cycles typically lost when using PIO. The DMA controller will inform the system when its current operation has been completed by issuing an interrupt signal. Although the data is still transferred 1 memory unit at a time from the device, the transfer to main memory now circumvents the CPU because the DMA controller can directly access the memory unit.

### Steps involved in the mode of DMA transfer are as follows.

• The device wishing to perform DMA asserts the processors bus request signal.
• The processor completes the current bus cycle and then asserts the bus grant signal to the device.
• The device then asserts the bus grant ack signal.
• The processor senses in the change in the state of the bus grant ack signal and starts listening to the data and address bus for DMA activity.
• The DMA device performs the transfer from the source to the destination address.
• During these transfers, the processor monitors the addresses on the bus and checks if any location modified during DMA operations is cached in the processor. If the processor detects a cached address on the bus, it can take one of the two actions:
• Processor invalidates the internal cache entry for the address involved in the DMA write operation
• Processor updates the internal cache when a DMA write is detected
• Once the DMA operations have been completed, the device releases the bus by asserting the bus release signal.
• The processor acknowledges the bus release and resumes its bus cycles from the point it left off.

The 8085 microprocessor has two pins available for the DMA mode of I/O communication: HOLD (Hold) and HLDA (Hold Acknowledge).

• HOLD: This is an active-high input signal to the 8085 from another master requesting the use of the address and data buses. After receiving the HOLD request, the Microprocessor relinquishes the buses in the following machine cycle. All buses are tri-stated and a Hold Acknowledge signal is sent out. The Microprocessor regains control of buses after HOLD goes low.
• HLDA: This is an active-high output signal indicating that the MPU is relinquishing control of the buses. Typically, an external peripheral such as a DMA controller sends a request for a high signal to the HOLD pin. The processor completes the execution of the current machine cycle; floats (high impedance state) the address, the data, and the control lines; and sends the Hold Acknowledge (HLDA) signal. The DMA controller takes control of the buses and transfers data directly between source and destination, thus bypassing the microprocessor. At the end of data transfer, the controller terminates the request by sending a low signal to the HOLD pin, and the microprocessor regains control of the buses.

You can avail of Online Classroom Program for all AE & JE Exams:

## Online Classroom Program for AE & JE Exams (12+ Structured LIVE Courses and 160+ Mock Tests)

You can avail of BYJU'S Exam Prep Test Series specially designed for all AE & JE Exams:

## BYJU'S Exam Prep Test Series AE & JE (160+ Mock Tests)

Thanks,

Team BYJU'S Exam Prep

Sahi Prep Hai to Life Set Hai !!!

Download BYJU'S Exam Prep APP , for best Exam Preparation , Free Mock Test, Live Classes