Analysis of operating mode of BJT
Method-1
To determine the mode of operation of a BJT, the following steps are followed.
Step 1 :- Let Assume that the transistor is biased on the forward active mode,
In this case put
V_{BE} = V_{BE(ON)}, I_{B} > 0 and I_{C} = βI_{B}
Step 2 :- Evaluate the linear circuit with these assumption.
Step 3 :- Find the each terminal voltagesi.e., V_{B}, V_{C} and V_{E}.
Step 4 :- Now, the BJT can be considered as two diodes connected back to back as shown below in figure 1
Step 5 :- Inspect whether the diodes are forward biased or reverse biased
Step 6 :- Conclude the operating mode of transistor for the condition according given in table 1.
Method-2
The mode of operation of the Transistor is found by follwing the given steps.
Step 1 :- Assume the transistor is biased in the forward active mode. In this case put
V_{BE} = V_{BE(ON)}, I_{B}>0 and I_{C} = βI_{B}
Step 2 :- Evaluate the linear circuit with these assumption.
Step 3 :- Determine the operating region by following condition
V_{CE} > V_{CE} _{(sat)} Active region
V_{CE} < V_{CE} _{(sat)} saturation region
Method-3
To determine the mode of operation of a BJT, the following steps are followed.
Step 1 :- Assume the transistor is biased in the forward active region. In this case put
V_{BE} = V_{BE(ON)}, I_{B }> 0 and I_{C} = βI_{B}
Step 2 :- Determine the collector current, (I_{C})_{active }for the transistor operating in active region.
Step 3 :- Determine the value of collector current (I_{C})_{sat} in saturation mode.
Step 4 :- Find the mode of operation by following the given below conditions.
(I_{C})_{sat} < (I_{C})_{active} Saturation
(I_{C})_{sat} > (I_{C})_{active} Active
Operating point of BJT
- From transistor characteristics, it is clear that a transistor functions most linearly when it is constrained to operate in its active region.
- To establish an operating point in the region it is necessary to provide approximate direct potentials and current, using external source.
- Once an operating point (also known as Quiescent or Q-point) is established, time varying excursions of input signal (base current, for example) should cause an output signal (Collector voltage as collector current) of the same waveform.
- If the output signal is not faithful reproduction of the input signal, for example, it is clipped on one side, then the operating point is unsatisfactory and should be relocated on the collector characteristics.
- Figure 3(a) shows the common emitter circuit (the capacitors have negligible reactance at the lowest frequency of operation of this circuit). Figure 3(b) gives the output characteristics of the transistor used in figure 3(a).
- Note that even if there are freedom to choose R_{C}, R_{L}, R_{b} and V_{CC}, it is not possible to operate the transistor everywhere in active region because various transistor ratings limit the range of useful operation.
The DC and AC load lines
The capacitance considered in the circuit of figure 3(a) is large enough so that they act as open circuits under DC conditions but short circuits at the lowest frequency of operation of the circuit. Since the capacitor are open-circuited under DC conditions so the circuit can be redrawn as shown below in figure 3(c)
.....(i)
- Equation (i) represents the dc or static load line of the circuit with a slope of –1/R_{C} as drawn in figure 3(b).
- If R_{L} = ∞ and if the input signal (base current) is large and symmetrical, operating point Q_{1} must be located at the center of the load line. In this way, the collector voltage and current may vary approximately symmetrical around the quiescent values V_{C} and I_{C}, respectively.
- If R_{L} ≠ ∞, however, an ac or dynamic load line must be considered.
- Since capacitors act as short circuits at input signal frequency, the effective load at the collector becomes R_{C} in parallel with R_{L}.
- Now, AC or dynamic load line is defined as a line that passes through the dc operating point Q_{1} and has a slope equal to 1/R'_{L} corresponding to the collector load. =R_{C}||R_{L, }Under AC conditions. This AC load line is indicated in figure 3(b).
Instability of collector current
From the above discussion, it is found that to obtain faithful reproduction of the input signal it should necessary to maintain a stable Q-point.
The collection current can be calculated by the following equation.
I_{c} = β I_{B} + (1+β) I_{co} …………(ii)
From equation (ii), It can be concluded that I_{c} is unstable due to the following reasons:
(i) Variations in I_{co}
I_{co} is the reverse saturation current of the collection function. It increases with an increase in temperature because of the increase in the concentration of minority carriers.
- If temperature increase by 1°C then I_{co} increases by 7%.
- For each 10°c rise in temperature I_{co}
Hence it is observed that variation in temperature causes change in I_{co} and as result, I_{c} also varies.
(ii) Variation in V_{BE}
When temp increased 1°C, V_{BE} decreased by 2.5 mV.
Hence, changes in temperature create change in V_{BE} due to which base current (I_{B}) changes. Hence from equ. (ii) it can be concluded that collection current I_{c} also varies.
(iii) Variation in β
β varies w.r.t transistor replacement or due to variation in temperature.
- When a transistor is replaced with another transistor, β value will vary because it is practically difficult to find two transistors having exactly same value of β.
- For a given transistor, β also increases with an increase in temperature.
Hence from the above discussion, it can be concluded that I_{c} is unstable due to variation in I_{co}, β and V_{BE} i.e
I_{c} = f (I_{CO}, V_{BE}, β) …………(iii)
From the above equation, It is clear that I_{c} is a function of I_{co}, β and V_{BE.}
By Applying partial differentiation on equation (iii),
ΔI_{c} = s.ΔI_{co} + s’ΔV_{BE} + s”Δβ ………….(iv)
Where s, s’ and s” are stability factors.
- From equation (iv), it can be conducted that for greater stability in I_{c}, ΔI_{c} should be smaller, which is possible when stability factors are smaller.
- Instability in I_{c} has two undesired effects:
(i) The operating point which changes along the load line may result in distorted output and some worst situations the operating point may move into cut off or saturation region.
(ii) Thermal runaway may occur which leads to damage of a BJT.
- Hence, collector current I_{c} should be made stable with either stabilization or compensation methods.
Procedure to find stability factor
Step 1: Find expression for I_{B} by applying KVL in a proper loop in the given circuit.
BJT biasing
Biasing is a technique to make the Q-point (Quiescent point or operating point) stable with respect to temperature variation.
Commonly used biasing circuits are:
(i) fixed bias circuit
(ii) collector to base bias circuit
(iii) self-bias circuit
Fixed bias circuit
In figure 4(a), the base current is derived from supply voltage V_{cc} by resister R_{B}. This type of biasing is called fixed bias as V_{cc} and R_{B} are fixed quantities.
The operating point Q_{1} is chosen on load line for a particular Base current I_{B} as shown in figure 4 (c)
By applying KVL in input loop,
Hence from above equ, Q-point (V_{CE}, I_{C}) is calculated for fixed I_{B}.
Stability factor
Disadvantage
- If β = 100, the stability factor is 101 and the collector current is 101 times that I_{CO}, reverse saturation current. Hence the stability factor for a fixed biased circuit is very high. So, it will be the least stable biasing arrangement.
Collector to base bias circuit
An improvement in bias stability is obtained if tapping for bias is taken from the collector terminal instead of from the collector supply point as shown in figure 5.
Applying KVL in input loop,
–V_{CC} + (I_{B} + I_{C}) R_{c} + I_{B}R_{B} + V_{BE} = 0
Now applying kVL in the output loop
–V_{cc} + R_{c}(I_{B} + I_{c}) + V_{CE} =0
With the help of above equ, operating point is calculated for given biasing circuit.
Stability factor
Advantage
- The stability factor is smaller than (β + 1), hence an improvement in stability is obtained over a fixed bias circuit.
Disadvantage
- The stability factor depends upon R_{C}. If R_{c }becomes smaller or zero, then the stability factor becomes very large and I_{C} does not remain stable.
- Resistance R_{B} connected from collector to base causes negative feedback due to which voltage gain of the amplifier's circuit decreases.
Self-bias or Voltage-Divider bias
- If the collector resistance R_{c} is very small, for example, in a transformer coupled circuit, then there is no improvement in stabilization in collector to base bias circuit over the fixed bias circuit.
- A circuit which can be used even if there is zero DC resistance in series with the collector terminal is self-biasing configuration of figure 6(a).
- The current in resistance R_{E} in emitter lead causes voltage drop which is in the direction of reverse biasing the emitter function.
- Since this function must be forward biased, the base voltage is obtained from supply through R_{1}, R_{2}
(Note: If R_{b} = R_{1}||R_{2} → 0, then base to ground voltage V_{BN} is independent of I_{CO}. Under these circumstances For best stability R_{1} and R_{2} must be kept as small as possible.)
- The given circuit in figure 6(a) can be simplified by using Thevenin’s theorem. Thevenin’s equivalent can be found between base and ground as shown in figure 6(b).
Now applying kVL in input loop
–V + I_{B} R_{b} + V_{BE} + (I_{B} + I_{C}) R_{E} = 0
By using _{ }
Stability factor
Important point
- S varies between 1 for small R_{b}/R_{E} and 1 + β for R_{b}/R_{E} → infinity
- A smaller value of R_{b}, better for stabilization.
(Note: even if R_{b} becomes zero, the value of S can’t be reduced below unity. Hence I_{c} always increases more than I_{co}.)
- As R_{b} to reduced which Q-point to held fixed, the current drawn R_{1}, R_{2} network from supply V_{cc}
- Also, if R_{c} is increased while R_{b} is held constant then V_{cc} must be increased to operate at the same Q-point.
- In either case, a loss of power (decreased efficiency) to disadvantage accompanies the improvement in stability.
- To avoid the loss of Ac (signal) gain because of feedback caused by R_{c}, this resistance is often passed by a large capacitance (> 10 μF), so that its reactance at frequencies under consideration is very small.
Basics of MOSFET
A Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is a field effect transistor (FET with an insulated gate) where the voltage determines the conductivity of the device. It is used for switching or amplifying signals. The ability to change conductivity with the amount of applied voltage can be used for amplifying or switching electronic signals. MOSFETs are now even more common than BJTs in digital and analog circuits.
Figure 1: Basic MOSFET structure
There are three possible regions for the working of the MOSFET.
- Triode Region
- Cut-off Region
- Saturation Region
Drain Current Equation:
Where μ_{n} = mobility of electron
C_{ox} = Capacitance of oxide layer
V_{DS} = drain to source voltage
Triode region
V_{DS} < V_{GS} – V_{t }, if V_{DS} (mV)
Current Saturation
V_{DS }≥ V_{GS} – V_{t}
(V_{DS})_{Sat} = V_{GS} – V_{t}
→ g_{m} should be more, so k_{n} should be more μ_{n} → faster, gain → higher.
→ A good MOSFET should have high value of k_{n}
_{}
Operating Condition for MOSFET
Operating Condition for N channel Enhancement type MOSFET:
Operating region | Required condition |
Cut off region | V_{GS }< V_{TN} |
Triode region | V_{GS }> V_{TN}, V_{DS }< V_{DS(sat)} (or) V_{DS} < V_{GS} – V_{TN} |
Saturation region | V_{GS }> V_{TN}, V_{DS }> V_{DS(sat)} (or) V_{DS }> V_{GS} –V_{TN} |
Operating Condition for P channel Enhancement type MOSFET:
Operating region | Required condition |
Cut off region | V_{SG} < |V_{TP}| |
Triode region | V_{SG} > |V_{TP}|, V_{SD} < V_{SD(sat)} or V_{SD} < V_{SG} + V_{TP} |
Saturation region | V_{SG} > |V_{TP}|, V_{SD} > V_{SD (sat)} or V_{SD} > V_{SG} + V_{TP} |
Operating Condition for N channel depletion type MOSFET:
Operating region | Required condition |
Cut off region | V_{GS} < V_{TN} |
Triode region | V_{GS} > V_{TN}, V_{DS} < V_{DS(sat)} (or) V_{DS} < V_{GS} – V_{TN} |
Saturation region | V_{GS} > V_{TN}, V_{DS} > V_{DS(sat)} (or) V_{DS} > V_{GS} – V_{TN} |
Operating Condition for P channel depletion type MOSFET:
Operating region | Required condition |
Cutoff region | V_{SG} < V_{TP} |
Triode region | V_{SG} > V_{TP}, V_{SD} < V_{SD(sat)} (or) V_{SD} < V_{SG} + V_{TP} |
Saturation region | V_{SG} > |V_{TP}|, V_{SD} > V_{SD(sat)} (or) V_{SG} + V_{TP} |
MOS Transconductance:
As a voltage-controlled source, a MOS transistor can be characterized by its transconductance
Various dependencies of g_{m}
_{}
Different biasing methods of MOSFET
There are four biasing methods for MOSFET: -
- Drain to gate bias
- Voltage divider bias
- Fixed bias
- Self bias
Drain to gate bias configuration: -
Drain to gate bias Configuration
DC Equivalent
DC Analysis-
Gate current , I_{G }=0
So, we have voltage drop across resistance R_{G} = V_{RG} = 0
Therefore, we get a direct connection between drain and source i.e.
V_{D} = V_{G}
_{}
_{Note:}
_{Drain to gate bias always enables MOSFET in saturation region}
For output circuit, we have
V_{DS} = V_{DD} – I_{D}R_{D}
Voltage divider bias configuration:
Voltage Divider Configuration
DC Equivalent
DC – ANALYSIS:
Using voltage divider, gate voltage is obtained by:
Applying KVL is loop 1, we get
V_{G} – V_{GS} – I_{D}R_{S} = 0
V_{GS} = V_{G} – I_{D}R_{S} …. (1)
Assume that MOSFET is in saturation, so we have I_{D} = K_{n} (V_{GS} – V_{TN})^{2}
By solving the quadratic equation, determine the value of V_{GS} or I_{D}, then apply KVL in source to drain loop
V_{DD} – I_{D}R_{D} – V_{DS} – I_{S}R_{S} = 0
V_{DS} = V_{DD} – I_{D} (R_{S} + R_{D})
If V_{DS} > V_{GS} – V_{TN}, then the transistor is indeed biased in saturation region, as we have assumed.
However, if V_{DS} < V_{DS (sat), }then transistor is biased in the non saturation region
Therefore from equation (1)
V_{GS} = V_{G} – I_{D}R_{S}
_{}
Fixed bias configuration:
Fixed bias Configuration
DC Equivalent
(In DC model, R_{G} is short and input impedance is very high i.e. (I_{G} ≃ 0))
DRAWBACK OF FIXED BIAS:
It is a dual battery design which makes it expensive and more space occupied bias Configuration.
Self bias configuration:
Self Bias Configuration
DC Equivalent
DC ANALYSIS:
0 = V_{GS} + I_{D}R_{S}
V_{GS} = – I_{D}R_{S}
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