Setup time and hold time -2 Starter Quiz

Output frequency of logic circuit shown below is ________GHz.

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output frequency (in KHz) is ________

If initially all J - K - Flipflops are cleared, Find the steady state output in decimal equivalent.

What should be the type of sequential circuit shown below to have ‘Race Around’ condition?

Consider a characteristic table for AB Flip Flop.

Suppose the above flip flop is implemented using JK flip flop then

Consider the circuit shown below, The resultant AB flip-flop is equivalent to

The truth table for AB flip-flop is shown below,

If this flip-flop using j-k flip-flop.

Then the input of j-k flip flop is