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GATE EC 2022:Digital Circuits Quiz 3
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Question 1
A one bit full adder takes 75 nsec to produce sum and 50 nsec to produce carry. A 4 bit parallel adder is designed using this type of full adder. The maximum rate of additions per second can be provided by 4 bit parallel adder is Ax106 additions/sec. The value of A is _____ .
Question 2
Consider the multiplexer based logic circuit shown in the figure.
Which one of the following Boolean functions is realized by the circuit?
Which one of the following Boolean functions is realized by the circuit?
Question 3
A 4-bit shift register circuit configured for right-shift operation, , is shown. If the present state of the shift register is ABCD = 1101, the number of clock cycles required to reach the state ABCD = 1111 is _________.
Question 4
The building block shown in fig. is a active high output decoder.
The output X is
The output X is
Question 5
consider the following circuits (assume all gates have a finite propagation delay)
1)
2)
3)
4)
Which of these circuits generate a periodic square wave output?
1)
2)
3)
4)
Which of these circuits generate a periodic square wave output?
Question 6
Consider a 3-bit number A and 2 bit number B are given to a multiplier. The output of multiplier is realized using AND gate and one bit full adders. If minimum number of AND gates required are X and one bit full adders required are then ________.
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May 21ESE & GATE EC