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GATE EC 2022: Analog Quiz 3 (App update required to attempt this test)

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Question 1

In the given figure , , the magnitude of voltage gain() will be ___

Question 2

In the circuit shown, V1 = 0 and V2 = Vdd. The other relevant parameters are mentioned in the figure. Ignoring the effect of channel length modulation and the body effect, the value of Iout is ___________ mA (rounded off to 1 decimal place).

Question 3

In the circuit shown, the breakdown voltage and the maximum current of the Zener diode are 20 V and 60 mA, respectively. The values of R1 and RL are 200 Ω and 1 kΩ, respectively. What is the range of Vi that will maintain the Zener diode in the ‘on’ state?

Question 4

An n-channel JFET, having a pinch-off voltage (Vp) of –5 V, shows a transconductance (gm) of 1 mA/V when the applied gate-to-source voltage (VGS) is – 3V. Its maximum transconductance (in mA/V) is

Question 5

In the circuit shown, the silicon BJT has Assume and Which one of the following statements is correct?

Question 6

For the given fixed-bias configuration, determine the parameters re & ro for its equivalent re  model of the transistor, if the input impedance of the network is 1 kΩ and the output impedance is 4 kΩ.

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V V Satya Narayana MadasuV V Satya Narayana MadasuMember since Sep 2020
Gate Qualified in 2018,2019,2020,2021| ISRO Exam qualified| AIR -672|Completed M.Tech in VLSI Design
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