GATE 2025 Digital Circuits Quiz 24

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Question 1

Consider the given circuit,
 
In this circuit, the race around

• ADoes not occur
• BOccurs when CLK = 0
• COccurs when CLK = 1 and A = B = 1
• DOccurs when CLK = 1 and A = B = 0

Question 2

A 3 bit module-8 ripple counter uses JK flip-flop. If the propagation delay of each FF is 40ns, the maximum clock frequency that can be used is equal to

• A20 MHz
• B10 MHz
• C8.33 MHz
• D4 MHz

Question 3

For each of the positive edge-triggered J-K flip flop used in the following figure, the propagation delay is ΔT


Which of the following waveforms correctly represents the output at Q₁?

• A
• B
• C
• D

Question 4

In the following figure, the J and K inputs of all the four Flip-Flops are made high. The frequency of the signal at output Y0 is

• A0.833 KHz
• B1.0 KHz
• C0.91 KHz
• D0.77 KHz

Question 5

The input A and clock applied to the D flip-flop are shown in figure below. The output Q is

 
          

• A(a)
• B(b)
• C(c)
• D(d)

Question 6

consider the circuit below with initial state Q₀ = 1, Q₁ = Q₂ = 0. The state of the circuit is given by the value of 4Q₂ + 2Q₁ + Q₀
   
which one of the following is the correct state sequence of the circuit?

• A1,3,4,6,7,5,2
• B1,2,5,3,7,6,4
• C1,2,7,3,5,6,4
• D1,6,5,7,2,3,4

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