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GATE 2025 Digital Circuits Quiz 23
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Question 1
The building block shown in fig. is a active high output decoder.
The output X is
The output X is
Question 2
A one bit full adder takes 75 nsec to produce sum and 50 nsec to produce carry. A 4 bit parallel adder is designed using this type of full adder. The maximum rate of additions per second can be provided by 4 bit parallel adder is Ax106 additions/sec. The value of A is _____ .
Question 3
The circuit shown below is:
Question 4
Consider the following full adder and input/output waveforms:
The most likely fault in the input, so that output waveform is correct is :
Question 5
A circuit is shown below:
The propagation time for each NAND gate is 10 nsec. What is the time required to get the output Y (in nsec). (Assume that all other gates are implemented using minimum number of NAND gates)
Question 6
A half adder is implement with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 μsec. A 4-bit ripple carry binary adder is implemented by using full adders. The total propagation delay of this 4-bit binary adder is
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Jan 4ESE & GATE EC
