GATE 2024 Subject Name Foundation Quiz 92

Which of the following is true about FSM?

Given finite state model (FSM) represents _______ gate.

A Mealy system produces a 1 output if the input has been ‘0’ for atleast by two consecutive clocks followed immediately by two consecutive 1’s. Then find minimum no. of states of system (S) and minimum number flip flops required (F).

The state diagram of a finite state machine (FSM) designed to detect an overlapping sequence of three bits is shown in the figure. The FSM has an input „In‟ and an output ‘Out’. The initial state of the FSM is S0.

If the input sequence is 10101101001101, starting with the left-most bit, then the number times ‘Out’ will be 1 is __________.