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GATE 2024 Digital Circuits Rank Booster Quiz 24

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Question 1

Consider the given circuit,

In this circuit, the race around

Question 2

A 3 bit module-8 ripple counter uses JK flip-flop. If the propagation delay of each FF is 40ns, the maximum clock frequency that can be used is equal to

Question 3

For each of the positive edge-triggered J-K flip flop used in the following figure, the propagation delay is ΔT

Which of the following waveforms correctly represents the output at Q₁?

Question 4

In the following figure, the J and K inputs of all the four Flip-Flops are made high. The frequency of the signal at output Y0 is

Question 5

The input A and clock applied to the D flip-flop are shown in figure below. The output Q is

Question 6

consider the circuit below with initial state Q₀ = 1, Q₁ = Q₂ = 0. The state of the circuit is given by the value of 4Q₂ + 2Q₁ + Q₀

which one of the following is the correct state sequence of the circuit?

Question 7

A 5-bit module – 8 ripple counter uses JK flip flop. If propagation delay of each flip flop is 75 ns, find maximum clock frequency that can be used (approx.)

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ESE & GATE EC Digital Circuits

Dec 7ESE & GATE EC