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GATE 2023 Digital Circuits Champion Quiz 5
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Question 1
In ADC, the full scale input voltage of 9 V with its resolution being 6 mV, then the number of bits used in the ADC _______.
Question 2
The I/P – O/P voltage for the standard TTL family are given by Vohmin = 2.6 V Volmax = 0.6V 
= 2V and 
= 0.4 V. The maximum – amplitude noise that can be tolerated when a high I/P is driving an input is
= 2V and = 0.4 V. The maximum – amplitude noise that can be tolerated when a high I/P is driving an input is Question 3
Which of following logic expression are shown
Question 4
A weighted resistor type digital to analog converter is designed as shown in the figure below. The input voltage is equal to 0 V for logic input ‘0’ and is equal to 5 V for logic input ‘1’. If the resolution of the digital to analog converter is equal to –0.3 V, then the value of RF (in Ω) is equal to
Question 5
What will be the output Y, if the input number 
as shown in the below digital circuit?
as shown in the below digital circuit?
Question 6
Consider the D-Latch shown in the figure, which is transparent when its clock input CK is high and has zero propagation delay. In the figure, the clock signal CLK1 has a 50% duty cycle and CLK2 is a one-fifth period delayed version of CLK1. The duty cycle at the output latch in percentage is ____.
Question 7
Three memory chips having equal 10 - bits address bus are of sizes 1KB, 2KB and 4KB.The data bus sizes of these three chips respectively
Question 8
Consider an excess-3 to BCD code converter as shown below which accepts excess-3 code as input and outputs corresponding BCD code
The simplified Boolean expression for the output bit Y is
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Sep 18ESE & GATE EC
