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BARC ECE 2019 : Digital Electronics Nuclear Quiz 2
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Question 1
For the output F to be 1 in the logic circuit shown, the input combination should be
Question 2
In the figure shown, the output Y is required to be Y = AB + . The gates G1 and G2 must be, respectively,
Question 3
The increasing order of speed of data access for the following devices is
(i) Cache Memory (ii) CDROM
(iii) Dynamic RAM (iv) Processor Registers
(v) Magnetic Tape
(i) Cache Memory (ii) CDROM
(iii) Dynamic RAM (iv) Processor Registers
(v) Magnetic Tape
Question 4
For the logic circuit shown in the below figure, the simplified Boolean expression for the output Y is
Question 5
A 3 bit module-8 ripple counter uses JK flip-flop. If the propagation delay of each FF is 40ns, the maximum clock frequency that can be used is equal to
Question 6
Given that:
The radix 8’s complement of Y is
The radix 8’s complement of Y is
Question 7
The range of signed decimal numbers that can be represented by 6-bit 1’s complement number is.
Question 8
An 8 bit DAC an output voltage of 4.0 V for input code of 1111 0001. The Resolution of DAC is
Question 9
the function realized by the given circuit is
Question 10
The initial state QDQT of the digital circuit given below is ‘01’
The state of circuit after 7 clock pulses is _______.
The state of circuit after 7 clock pulses is _______.
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