UPPCL AE Digital Electronics Quiz 5

Each flip-flop in a 4-bit ripple counter introduces a maximum delay of 40 n sec. The maximum clock frequency is

How many flip-flops are required to build a binary counter circuit to count from 0 to 1023?

In a positive edge triggered JK flip-flop, J = 1, K = 0 and clock pulse is rising, Q will be

Positive edge triggered SR flip flop with clock pulse = 0 and input combinations is S = 1, R = 0. The output state will be

A certain JK if has t_pd = 12 ns. What is the largest MOD counter, that can be constructed from these flipflops and still operate up to 10 MHz?

The 5 bit ripple counter which is composed of flip flops with a propagation delay of 20ns, would have the maximum counting speed of

It is required to build a ripple counter of modulus 20. The minimum number of flip-flop required is

A MOD-78 counter can be realized by using

A mod-3 counter is already available. To design a ‘divide by 6’ counter, further how many more flip-flops are required?