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Setup time and hold time Starter Quiz

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Question 1

Which of the following statements regarding setup and hold time is/are correct?

1) The maximum data path delay is used to determine if the setup time is met.

2) The minimum data path delay is used to determine if hold time is met.

3) The minimum data path delay is used to determine if the setup time is met.

4) The maximum data path delay is used to determine if hold time is met.

Question 2

The time required by the capacitor to get the charge of the input voltage applied to sample and hold circuit is called:

Question 3

For the components in the sequential circuit shown below, tpd is the propagation delay, tsetup is the setup time, and thold is the hold time. The maximum clock frequency (rounded off to the nearest integer), at which the given circuit can operate reliably, is …. MHz.

Question 4Multiple Correct Options

Binary shift registors are

Question 5

A 4-bit-16 ripple counter uses J-K flip-flop. If the propagation delay of each flip-flop is 50 nanoseconds, the maximum clock frequency that can be used is equal to:

Question 6

A ripple counter is made with three positive edge triggered flip-flops. If the output of previous lower significant bit flip-flop is used as a triggering clock pulse of the next higher significant bit flip-flop, then the resultant counter is a

Question 7

The 5 bit ripple counter which is composed of flip flops with a propagation delay of 20ns, would have the maximum counting speed of
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Jul 15ESE & GATE EE