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Paging II Starter Quiz

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Question 1

Suppose that you wish to design a virtual memory system with the following characteristics, the size of a page table entry is 32 bits, each page table must fit into a single physical frame and the system must be 35 bits. Suppose you decide to use a multilevel paging scheme with no more than two levels of page tables. What is the minimum page size your system must have?

Question 2

Assuming a page size 4 KB and that page table entry takes 4 bytes, how many levels of page tables would be required to map a 64-bit address space if every page table fits into a single page?

Question 3

Which of the following options is correct?

Question 4

Consider a system that has main memory access time is 30ns and page fault service time is 300ns and the page hit ratio 85% then what is the effective main memory access time?

Question 5

In a virtual memory system the size of virtual address is 20-bits and page size is 1 K bytes. The CPU generates a virtual address (6E752)H. To which page number this virtual address should belong:
(H denotes hexadecimal)

Question 6

In the demand paging memory, a page table is held in registers. If it takes 1000 ms to service a page fault and if the memory access time is 10 ms, what is the effective access time for a page fault rate of 0.01?

Question 7

A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.
What is the size of a page in KB in this computer?
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