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National Champion Test -GATE 2018 EE: Digital Circuit

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Question 1

A person wants to design a

multiplexer using only NAND gates. If NAND gates with any number of inputs are available, then total number of NAND gates required are ________.

Question 2

A series R-L-C circuit is connected to a d.c. source at t = 0. The transient voltage response across capacitor C shows no oscillations. Then

Question 3

The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater than the 2-bit input B. The number of combinations for which the output is logic 1, is

Question 4

A 4 × 1 MUX is used to implement a 3–input Boolean function as shown in figure. The Boolean function F (A, B, C) implemented is

Question 5

In INTEL 8085 Microprocessor after execution of XRA A instruction bits present in flags
$Description: E:\Gate\Gate-EE-14-Dec\12_Mprocesor_EMT_BL-done_files\image061.jpg$ are _________.
For Example:
If $Description: E:\Gate\Gate-EE-14-Dec\12_Mprocesor_EMT_BL-done_files\image062.png$
$Description: E:\Gate\Gate-EE-14-Dec\12_Mprocesor_EMT_BL-done_files\image063.png$
$Description: E:\Gate\Gate-EE-14-Dec\12_Mprocesor_EMT_BL-done_files\image064.png$
$Description: E:\Gate\Gate-EE-14-Dec\12_Mprocesor_EMT_BL-done_files\image065.png$
Then answer is abcde

Question 6

A JK flip flop can be implemented by T flip-flops. Identify the correct implementation.

Question 7

The logical gate implemented using the circuit shown below where.V₁ and V₂ are inputs (with 0 V as digital 0 and 5 V as digital 1) and V_out, is the output is

Question 8

Consider the program given below :
MOV A, C
STC
CMC
DCR C
Let, the content of register C is 00 H initially and the above instructions are executed, then content of register C and flag register is respectively

Question 9

For the ring counter shown in below, find the steady state sequence if the initial state of the counters is 1110 (i.e., Q₃, Q₂, Q₁, Q₀ =1110). Determine the MOD number of the counter.

Question 10

A sample-and-hold (S/H) circuit, having a holding capacitor of 0.1 nF, is used at the input of an ADC (analog-to-digital converter). The conversion time of the ADC is 1μsec, and during this time, the capacitor should not lose more than 0.5% of the charge put across it during the sampling time. The maximum value of the input signal to the S/H circuit is 5V. The leakage current of the S/H circuit should be less than

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ESE & GATE EE Digital Electronics

Jul 6ESE & GATE EE