Instruction Pipelining - Practice GATE 2024 Fundamental Quiz

The different stages of RISC pipeline will include:

A non-pipeline processor has a clock rate 4 MHz and an average CPI of 5. An upgrade to the processor introduces 5 stage pipeline. However due to internal delay the clock rate of the new processor has to be reduces to 3 MHz. What is the speed-up of pipeline over non-pipeline?(upto 1 decimal)

Consider a 5-stage pipeline with stage delays 1 ns, and 1.5ns. If there are 2 stall cycles for every 5 instructions, the average pipeline cycle time (in ns) is ______. [Round off to 1 Decimal Place]

Consider 4 stage instruction pipeline executed on a system:

If all instructions are executed only once, what is the throughput of system?

Consider a 5 stages instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle time overhead of pipelining. When application is executed on 5 stage pipeline, then how many instructions incur 3 pipeline stall cycles if the speedup achieved with respect to non pipeline is 3 _________.