NIELIT 2023: Instruction pipelining

Consider a 33 MHz CPU based system. What is the number of wait states required if it is interfaced with a 60 ns memory? Assume a maximum of 10 ns delay for additional circuitry like buffering and decoding.

A pipeline is having speed up factor as 10 and operating with efficiency of 80%. What will be the number of stages in the pipeline?

The technique used to store programs larger than the memory is ____________

A non-pipeline processor has a clock rate 4 MHz and an average CPI of 5 . An upgrade to the processor introduce 5 stage pipeline. How ever due to internal delay the clock rate of the new processor has to be reduces to 3 MHz. What is the speed-up of pipeline over non-pipeline?

Comparing the time T1 taken for a single instruction on a pipelined CPU, with time T2 taken on a non-pipelined but identical CPU, we can say that __________?