Due to resistance at the input terminals of a CE amplifier, which of the following statements in not correct?
Question 2
In BJT biasing, α is the common-base, short-circuit, amplification factor; and β is the common-emitter, forward current, amplification factor. Determine the relationship between α and β.
Question 3
In an NMOS circuit, Vt = 4 V and VGS ranges from 7.5 to 10 V. The channel to be continuous, finds the largest value of VDS?
Question 4
In a voltage divider bias circuit what will be the equivalent Vgsq.
Question 5
Which statement describes op-amp running in open-loop configuration that amplifies signal?
Question 6
The input signal Vin shown in the figure is a 1 KHz square wave voltage that alternates between +7V and -7V with a 50% duty cycle. Both transistors have the same current gain, which is large. The circuit delivers power to the load resistor RL. What is the efficiently of this circuit for the given input? Choose the closest answer.
Question 7
In the circuit shown below, Q1 has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If Vcc is +5V, X and Y are digital signals with 0 V as logic 0 and Vïas logic 1, then the Boolean expression for Z is
Question 8
The op-amp shown in the figure has a finite gain A = 1000 and an infinite input resistance. A step voltage Vi = 1 mV is applied at the time t = 0 as shown. Assuming that the operational amplifier is not saturated, the time constant (in millisecond) of the output voltage V0 is
Question 9
A waveform generator circuit using OPAMPs is shown in the figure. It produces a triangular wave at point ‘P’ with a peak to peak voltage of 5V for vi = 0V.
Question 10
The circuit shown in below, is equivalent to a load of
at the input terminals of a CE amplifier, which of the following statements in not correct? 
