Time Left - 15:00 mins

GATE CS 2022 : Computer Organization Quiz-7

Attempt now to get your rank among 136 students!

Question 1

For inclusion to hold between two cache levels L1 and L2 in a multi–level cache hierarchy, which of the following are necessary?
I. L1 must be a write–through cache
II. L2 must be a write–through cache
III. The associativity of L2 must be greater than that of L1
IV. The L2 cache must be at least as large as the L1 cache

Question 2

The program is executed from Main Memoryuntil it attempts to reference a page that is still in auxiliary memory, this condition is called as ____________

Question 3

A 17 way set associative cache has 16 byte blocks and 32 bit byte addressable memory. The cache size is 17408 bytes. How many total bits required for both tag and word offset for any CPU reference?

Question 4

How many 128 X 8 RAM chips are needed to provide a memory capacity of 2048 bytes?

Question 5

Consider a system having 60% of its instruction is write operations. Hit rate for read operation is 0.7. Cache access time and main memory access time is 3 ns and 75 ns respectively. Then average access time of the system in ns if write through policy is used.

Question 6

Consider a 2-way set associative cache with 256 blocks and uses LRU replacement, Initially the cache is empty. Conflict misses are those misses which occur due the contention of multiple blocks for the same cache set. Compulsory misses occur due to first time access to the block. The following sequence of accesses to memory blocks.
(0,128,256,128,0,128,256,128,1,129,257,129,1,129,257,129) is repeated 10 times. The number of conflict misses experienced by the cache is __________.

136 attempts
0 upvotes
0 comments

Tags :

GATE & PSU CS Computer Organization and Architecture

Nov 2GATE & PSU CS