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GATE CS 2022 : Computer Organization Quiz-5

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Question 1

A pipelined processor uses 5 stages with execution time of 3,4,3,2,4 cycles respectively. The corresponding non-pipelined processor uses 8 clock cycles to complete a instruction (ignore buffer delay). Calculate speedup assuming that a very large number of instruction are to be executed.

Question 2

In the pipeline diagram shown, which cycle indicates that pipeline is full?

Question 3

Consider a processor in which every instruction goes through 6 phases of processing. Instruction fetch (IF), Instruction decode(ID), register fetch (RF), execution (EX), data memory access (DMEM) and register writeback (WB). The phase latencies are : 2ns, 1ns, 1ns, 1ns, 2ns, 1ns respectively. Designers of this processor are planning to design the processor as a 3 stage pipeline (call the stages S1, S2 and S3). There are multiple design choices for composing these 3 pipeline stages. For ex : One choice could be to put IF in S1, ID in S2 and the rest 4 phases in S3. Ignoring all the delays in pipeline registers, the largest frequency achievable by this 3 stage pipeline is :

Question 4

Consider a 4-stages pipeline with respective stage delays of (10ns, 5ns, 20ns & 15ns) .What is the efficiency of the pipeline when the number of tasks are significantly larger than the number of stages?

Question 5

Consider the 10 stages pipeline operated with 5ns clock, which allows all instruction except memory referenced instruction. Memory references instruction penalty is 5 cycles. Program contain 30 percent memory instruction. What is the speedup?

Question 6

Consider a 4- Stage pipeline with respective stage delays of 20ns, 30ns, 40ns & 60ns. Interface register is used between the stages which is having delay of 5ns.What is the performance gain when very large no of instructions are executed _______?
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