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GATE CS 2018 - Computer Organization Quiz 6 (Memory Organization-1)

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Question 1

For inclusion to hold between two cache levels L1 and L2 in a multi–level cache hierarchy, which of the following are necessary?
I. L1 must be a write–through cache
II. L2 must be a write–through cache
III. The associativity of L2 must be greater than that of L1
IV. The L2 cache must be at least as large as the L1 cache

Question 2

Consider a machine with a 2–way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache is managed using 32 bit virtual addresses and the page size is 4 Kbytes. A program to be run on this machine begins as follows:

double ARR[1024][1024];

int i, j; /*Initialize array ARR to 0.0 */

for(i = 0; i < 1024; i++)

for(j = 0; j < 1024; j++)

ARR[i][j] = 0.0;
The size of double is 8 Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre–fetching is done. The only data memory references made by the program are those to array ARR.
The total size of the tags in the cache directory is

Question 3

More than one word is put in one cache block to

Question 4

The program is executed from Main Memoryuntil it attempts to reference a page that is still in auxiliary memory, this condition is called as ____________

Question 5

A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is

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