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GATE CS 2018 - Computer Organization Quiz 5 (Instruction Pipelining-2)

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Question 1

The performance of a pipelined processor suffers if

Question 2

In the pipeline diagram shown, which cycle indicates that pipeline is full?

Question 3

Consider a pipelined processor with the following four stages:
IF: Instruction Fetch
ID: Instruction Decode and Operand Fetch
EX: Execute
WB: Write Back
The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage depends on the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?
ADD R2, R1, R0 R2

R1 + R0
MUL R4, R3, R2 R4

R3 * R2
SUB R6, R5, R4 R6

R5 - R4

Question 4

A 4-stage pipeline has the stage delays as 150, 120, 160 and 140 nanoseconds respectively. Registers that are used between the stages have a delay of 5 nanoseconds each. Assuming constant clocking rate, the total time taken to process 1000 data items on this pipeline will be

Question 5

A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD and SUB instructions, 3 clock cycles for MUL instruction, and 6 clock cycles for DIV instruction respectively. Operand forwarding is used in the pipeline. What is the number of clock cycles needed to execute the following sequence of instructions?
I₀ : MUL R₂, R₀, R₁ ; R₂R₀ * R₁
I₁ : DIV R₅, R₃, R₄ ; R₅R₃/R₄
I₂ : ADD R₂,R₅, R₂ ; R₂R₅ + R₂
I₃ : SUB R₅, R₂, R₆ ; R₅R₂ – R₆

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GATE & PSU CS Computer Organization and Architecture

Feb 19GATE & PSU CS