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GATE CS 2018 - Computer Organization Quiz 4 (Instruction Pipelining-1)

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Question 1

In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is

Question 2

Which of the following are NOT true in a pipelined processor?
I. By passing can handle all RAW hazards.
II. Register renaming can eliminate all register carried WAR hazards.
III. Control hazard penalties can be eliminated by dynamic branch prediction.

Question 3

Question 4

Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.

What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?

Question 5

Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency.
P1 : Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns.
P2 : Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns.
P3 : Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns.
P4 : Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns.
Which processor has the highest peak clock frequency?

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GATE & PSU CS Computer Organization and Architecture

Jun 25GATE & PSU CS