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GATE CS 2018 - Computer Organization Quiz 2 (ALU)

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Question 1

Suppose a processor does not have any stack pointer register. Which of the following statements is true?

Question 2

For a pipelined CPU with a single ALU, consider the following situations
I. The j + 1-st instruction uses the result of the j-th instruction as an operand
II. The execution of a conditional jump instruction
III. The j-th and j + 1-st instructions require the ALU at the same time
Which of the above can cause a hazard?

Question 3

Which of the following must be true for the RFE (Return from Exception) instruction on a general purpose processor?
I. It must be a trap instruction
II. It must be a privileged instruction
III. An exception cannot be allowed to occur during execution of an RFE instruction

Question 4

Consider the following data path of a simple non-pile lined CPU. The registers A,B, A₁, A₂, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bitregisters. The MUX is of size 8 × (2:1) and the DEMUX is of size 8 × (1:2). Each memory operation takes 2 CPU clock cycles and uses MAR (Memory Address Register) and MDR (Memory Date Register). SP can be decremented locally

The CPU instruction “push r”, where = A or B, has the specification
M [SP] ←r
SP ←SP – 1
How many CPU clock cycles are needed to execute the “push r” instruction?

Question 5

The amount of ROM needed to implement a 4 bit multiplier is

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GATE & PSU CS Computer Organization and Architecture

Jun 25GATE & PSU CS