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GATE 2025 EDC Evaluation Quiz 4
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Question 1
Assume that mobility of electrons in silicon at T=300 K is μn =1300 cm2 /V-sec. Also assume that the mobility is limited by thermal motion of atoms and varies with temperature. Then the electron mobility (in cm2/V-sec) at T = 400K is (approximate value)
Question 2
The minority carrier hole diffusion coefficient is D p = 12cm2/s and majority carrier electron diffusion coefficient is D n = 48 cm2/s. If the sum of electron and hole mobility is 100 cm2/V-sec, then electron mobility is _____ (cm2/V-sec)
Question 3
Figure shown below is a plot of the steady state carrier concentration inside a p-n junction maintained at room temperature.
What is the condition of the diode?
What is the condition of the diode?
Question 4
An ideal one-sided silicon n+p junction has uniform doping on both sides of the abrupt junction. The doping relation is 
The built-in potential barrier is 
. The applied reverse bias voltage is 
.The space charge width is:-
(ni= 1.5 x 1010 cm-3,εr=11.7)
The built-in potential barrier is . The applied reverse bias voltage is .The space charge width is:-(ni= 1.5 x 1010 cm-3,εr=11.7)
Question 5
An ideal MOS capacitor has a p–type substrate with a doping concentration of 1016 cm–3 Boron atoms / cm3. If a positive DC gate voltage is applied, then the maximum width of space charge region that can exist in the substrate is ________ mm.
(Assume, eSi = 1.04 × 10–12 F /cm, kT/q = 26 mV and ni = 1.5 × 1010 cm–3)
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