GATE 2024 Digital Electronics Foundation Quiz 83

If initially all J - K - Flipflops are cleared, Find the steady state output in decimal equivalent.

What should be the type of sequential circuit shown below to have ‘Race Around’ condition?

Consider a characteristic table for AB Flip Flop.

Suppose the above flip flop is implemented using JK flip flop then

On the 3^rd clock pulse of a 4- bit Johnson counter is 1110 (Q₃ Q₂ Q₁ Q₀). Find the initial sequence in decimal number Format.

For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of the MOD-256 counter? (in MHz)