GATE 2024 Computer Organization & Architecture Foundation Quiz 81

Consider a machine with a byte addressable main memory of 1 petabyte divided into block size of 32 bytes. Assume that a direct mapped came having 2K caches lines is used with this machine. The size of the tag field in bits is ______.

Consider a system with a single external cache; the access time of cache is 15 ns and that of the main memory is 50 ns. If effective memory access time is 50 percent of the main memory access time, then what is the hit ratio of the cache?

Consider a 2-way set associative cache with 8 cache blocks. If the memory block requests are accessed 2 times in the following order 0, 4, 8, 4, 0, 4, 8, 4, 3, 15, 19, 3, 15, 19, If LRU replacement policy is used, then find the total number of misses?

Consider a 128 KB, 4-way set associative cache organised into a 64 B blocks. The set number(in decimal) to which the memory address 0×4CB410 is mapped to is?

Consider a 32-bit microprocessor that has an on chip 16 Kbyte four way set associative cache. Assume that cache has a line size of four 32-bit words. Which of the following set number in the cache to which the word from memory location FFFAE8FA is mapped?