GATE 2024 Computer Organization & Architecture Foundation Quiz 81

A hypothetical CPU takes 4 clock cycles for 1 MIPS on average for any instruction. The memory access time is 1 clock cycle for each word. What is the peak date transfer rate?

Consider a 5 ns clock cycle processor which consumes 8 cycles for a load instruction, 7 cycles for ALU operation, and 4 cycles for branch operation. The relative frequencies of this instruction are 40%, 40%, and 20%, respectively. Another ideal processor with CPI=1 and a clock speed of 1.6 ns is used to execute the program. What is the speedup using the ideal processor over another?

Consider the following reservation table for a pipeline with stages S₁, S₂, and S₃.

The throughput of the pipeline is:

[Round off to 1 decimal place]

Consider an instruction pipeline with five stages without any branch prediction. The stages are: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 8 ns, 7 ns, 15 ns, 6 ns and 4 ns, respectively. A program consisting of 10 instructions is executed in this pipelined processor. Instruction I₄ is the only branch instruction, and its branch target instruction is I₉. If the branch is taken during the execution of this program and the branch target instruction I₉ is not completed until the current branch instruction completes, then the time (in ns) needed to complete the program is:-

A processor X₁ operating at 2 GHz has a standard 5-stage RISC instruction pipeline having a base CPI (cycles per instruction) of one without any pipeline hazards. For a given program P that has 30% branch instructions, control hazards incur 2 cycles stall for every branch. A new version of the processor X₂ operating at same clock frequency has an additional branch predictor unit (BPU) that completely eliminates stalls for correctly predicted branches. There is neither any savings nor any additional stalls for wrong predictions. There are no structural hazards and data hazards for X₁ and X₂. If the BPU has a prediction accuracy of 80%, the speed up (rounded off to two decimal places) obtained by X₂ over X₁ in executing P is____________.