GATE 2024 Computer Organization & Architecture Foundation Quiz 30

We have a single stage, non-pipelined machine and a pipelined machine with 5 pipeline stages. The cycle time of the former is 5ns and the latter is 1ns.

Assuming no stalls, what is the speedup of the pipelined machine over the single stage machine?

Any condition that causes a processor to stall is called as _________

ALU operations are performed in which stage of the pipeline?

Which hazard occurs when instruction J tries to write data before instruction, I reads it.

A compiler designer is trying to decide between two code segments for a particular machine. The hardware designers have provided the following data below about the CPI for each class, and the instruction counts being considered for each code sequence.

Which of the following is true ?