Time Left - 15:00 mins

GATE 2023 Digital Logic Quiz 44

Attempt now to get your rank among 92 students!

Question 1

Let the two counter be modulus-7 & modulus-3 counter and both are cascaded with 7MHz clock frequency applied on it, then what is the lowest frequency in KHz?

Question 2

32 bit − Shift register operated with 1 MHz clock. How much time is required to it, to load & Read the data in SIPO (Serial In Parallel Out)?

Question 3

Given a 5-bit serial in parallel out right shift register shown in figure below, initial content of register is

After how many clock pulses content of register will become 1 1 1 1 1?

Question 4

If the input is 010010, the final value stored in shift register will be_______

Question 5

A 4-bit synchronous UP counter is holding a state 0101. What will be the count after 27^th clock pulse?

Question 6

Given a sequential circuit:

If initial state Q1 Q2 Q3 = 1 0 1 after how many cycles does it get to the same value?

92 attempts
0 upvotes
0 comments

Tags :

GATE & PSU CS Digital Logic

Jun 16GATE & PSU CS