GATE 2023 Computer Organization & Architecture Rank Booster Quiz 5

Let T₁ be the throughput of Burst mode of DMA, T₂ be the throughput of cycle stealing mode of DMA and T₃ be the throughput of Transparent DMA. What is the relation between T₁, T₂ and T₃?

A DMA is transferring characters to processor from a device transmitting at 8000 bits per sec. Assume DMA using cycle stealing mode. If processor needs access to main memory once every micro second. The percentage processor be slow down due to DMA activity is ______ (in %).

A DMA controller has five channels. The controller can request a 32-bit word every 20 nsec. A response takes equally long. How fast does the bus have to be to avoid being a bottleneck [in MBps]? [in integer]

A hard disk with a transfer rate of 1 kbps is constantly transferring data to memory using DMA cycle stealing mode. The size of the data transfer is 16 bytes. The processor runs at 400 kHz clock frequency. The DMA controller requires 10 cycles for initialization of operation and transfer takes 2 cycles to transfer one byte of data from the device to the memory. What is the percentage of processor time blocked during this DMA operation?

Consider a system in which I/O device has a data transfer rate of 20KB/s and employs DMA. Bus cycle takes 200 ns. Transfer of bus control in both directions takes 120 ns. Data is transferred 1 byte at a time. Suppose if DMA cycle stealing mode is used, for how long (in microseconds) bus would be tied up if a block of 256 bytes is transferred? [In integer]

A hypothetical DMA controller is designed to transfer the data from I/O device to main memory under burst mode. The count register size is 32 bit and gets the control of the system buses 3 times then the maximum size of the data transferred by the controller in Giga bytes is ________.