GATE 2024 Computer Organization & Architecture Rank Booster Quiz 3

Any condition that causes a processor to stall is called as _________

Which hazard occurs when instruction J tries to write data before instruction, I reads it.

A compiler designer is trying to decide between two code segments for a particular machine. The hardware designers have provided the following data below about the CPI for each class, and the instruction counts being considered for each code sequence.

Which of the following is true ?

Identify the write-read, write-write, and read-write dependencies in the instruction sequence below.

L1: R1 = 100

L2: R1 = R2 + R4

L3: R2 = R4 - 25

L4: R4 = R1 + R3

L5: R1 = R1 + 30

Which of the following is true ?

Consider a 5 stage pipeline with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Write Back (WB) and Memory Access (MA) having latencies (in ns) 3, 8, 5, 6 and 4 respectively. What is average CPI of non-pipeline CPU when speed up achieved with respect to pipeline is 4?

Consider a non-pipelined processor with a clock rate of 5 Ghz and an average CPI of 5. The processor is upgraded to 5 stage pipeline processor and clock rate reduced to 4 GHz. The speedup achieved in the pipelined processor is ________.

Consider two pipelined processor A and B where processor A is having 8 stages of uniform delay of 2 ns. Processor B is having 5 stages with respective delays of 2 ns,6 ns,3 ns,4 ns and 2 ns. How much time is saved when the 100 tasks are pipelined using A instead of B?