GATE 2023 Computer Organization & Architecture Quiz 15

Which of the following statements is incorrect?

Statement 1-DMA breakpoints can occur after the decoding phase.

Statement 2-Interrupt did not use in the case of DMA data transfer mode.

Statement 3-DMA can operate either in burst mode or cycle stealing mode.

Statement 4-A processor checks for interrupts before executing a new instruction.

Separate instructions are used to address I/O devices and the main memory in the approach of ______.

1. Isolated I/O
2. Memory-mapped I/O

Consider 1 MBps IO device, which is interfaced to processor in a cycle stealing mode of DMA. Whenever 32 bytes data is available in buffer, transfer it main memory. Main memory cycle time is 0.5 micro-seconds, and word length of processor is 16 bit. How much % of CPU time is consumed in DMA operation?

A hypothetical DMA controller is designed to transfer the data from I/O device to main memory under burst mode. The count register size is 32 bit and gets the control of the system buses 3 times then the maximum size of the data transferred by the controller in Giga bytes is ________.

Which of the following best characterizes about memory mapped I/O?