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GATE 2023 Computer Organization & Architecture Quiz 13

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Question 1

Consider execution of 100 instructions on a 5 stage pipeline. Let P be the probability of an instruction being a branch. What must be the value of P such that speed up is atleast 4?
(Assume each stage takes 1 cycle to perform it’s task and branch is predicted on fourth stage of the pipeline)

Question 2

Consider the 10 stages pipeline operated with 5ns clock, which allows all instruction except memory referenced instruction. Memory references instruction penalty is 5 cycles. Program contain 30 percent memory instruction. What is the speedup?

Question 3

Consider a 5 stage pipeline with Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Write Back (WB) and Memory Access (MA) having latencies (in ns) 3, 8, 5, 6 and 4 respectively. What is average CPI of non-pipeline CPU when speed up achieved with respect to pipeline is 4?

Question 4

For a given system pipeline, speedup factor is 8.4 and it operates at 100MHZ with 60% efficiency. The number of stages in pipelines are _________.

Question 5

Consider a machine with 10 ns clock and it takes 4 clock cycle per ALU instruction, 5 clock cycle per branch instruction, 6 clock cycle memory instruction. There exists 40% ALU instruction, 20% branch instruction, and 40% memory instruction. What is speedup of pipeline system if overhead is 2 ns ?

Question 6

Consider a 4-stages pipeline with respective stage delays of (10ns, 5ns, 20ns & 15ns) .What is the efficiency of the pipeline when the number of tasks are significantly larger than the number of stages?

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GATE & PSU CS Computer Organization and Architecture

Aug 30GATE & PSU CS