GATE 2022: Digital Logic Quiz-11 for GATE & PSU CS Exams

Question 1

The number of minterms after minimizing the following Boolean expression is

[ D’ + AB’ + A’C + AC’D + A’C’D]’

Question 2

The minimized expression for the given K-MAP (X: don’t care] is

Question 3

For the map shown below, the minimized logical expression in sum of product (SOP) form is

Question 4

A switching circuit has four inputs as shown below :

The output ‘F ’ is ‘1’ only when the product (S₁ × S₂)₁₀ is less than or equal to ‘2’. The minimized form of F is

Question 5

Consider the following K-Map -

Which of the following is not the dual of the minimized expressions formed using the above K-map?
I) (A'+C+D') (B+C+D) (A+C'+D) (B'+C'+D')
II) (A'+B'+D') (A'+B+C) (A+B+D) (A+B'+C')
III) (A'+B'+D') (A'+B+C') (A+B+D) (A+B'+C')

Question 6

Consider the following values, using the IEEE 754 single precision floating-point format. What is
the equivalent value as a decimal number?

0101 1100 1010 0100 0100 0000 0000 0000

Question 7

Consider the following floating point format:

The exponent is formatted using excess 16 notation with an implied base of 2. If the contents are:
Sign: 0
Exponent: 10111
Mantissa: 1100100000
What is the exponent value expressed by the above format?

Question 8

Without any additional circuitry, an 8 : 1 MUX can be used to obtain?

Question 9

The minimum number of 2 × 1 MUX required to implement a half-subtractor circuit when only basic inputs 0, 1, A and B are available is

Question 10

A MUX is a combinational circuit that selects binary information from one to many input lines & direct it to the single output line. Consider the 64 X 1 MUX being implemented using the 2 X 1 MUX. So what is the number of mux present in the level 4th of the above circuit?

Question 11

A gate has two inputs (A, B) and one output (Y) is implemented using a 4 × 1 MUX as shown in the figure below:

If the function ‘Y’ = B then the select line will be:

Question 12

To realise a 128x1 MUX , how many 4x1 MUX are required _____________

Question 13

A synchronous counter is designed using J-K FF, X-Y FF and D-FF as shown below. X-Y FF truth table is

If the initial content of the counter is 001 at Q₂ , Q₁, Q₀, after how many number of clock pulses , counter is back to the same state :

Question 14Multiple Correct Options

An AB Flip-flop is designed using JK FF which of the following can be Boolean function for the input of JK Flip-Flop, consider the truth table of AB Flip-flop as given below: (Multi Select Question)

Question 15

A twisted ring counter is implemented using 4 D-flip flops. If each FF has 40nsec of delay, what is the maximum usable clock frequency which ensures that there are no timing violations?