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GATE 2020 : Digital Logic Quiz 7
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Question 1
Let k = 2n. A circuit is built by giving the output of an n-bit binary counter as input to an n to 2n bit decoder. This circuit is equivalent to a
Question 2
The initial contents of the 4-bit serial-in-parallel-out, right-shift, Shift Register shown in the figure is 0110. After three clock pulses are applied, the contents of the Shift Register will be
Question 3
The next state table of a 2-bit saturating up-counter is given below.
The counter is built as a synchronous sequential circuit using T flip-flops. The expression for and are
The counter is built as a synchronous sequential circuit using T flip-flops. The expression for and are
Question 4
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.
If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
Question 5
Consider the following synchronous counter made up of JK, D and T flip-flops.
Find the modulus value of the counter.
Find the modulus value of the counter.
Question 6
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0,0,1,1,2,2,3,3,0,0,…) is__________.
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