GATE 2019 -National Champion Test : (Computer Organizations) (App update required to attempt this test) for GATE & PSU CS Exams

Question 1

Highly encoded schemes that use compact codes to specify a large number of functions in each micro-instruction is

Question 2

Horizontal micro-instructions have which of the following attributes?
1) Short formats
2) Limited ability to express parallel micro-operations
3) Considerable encoding of the control information

Question 3

A DMA module is transferring character to memory using cycle stealing, from a device transmitting at 12800 bps. The processor is fetching instructions at the rate of 4 million instructions per second. By how much (in %) will the processor slow down due to DMA activity?

Question 4

Consider the following statements.
I. It increases the maximum I/O transfer rate
II. It reduces the interface by the DMA controller in the CPU’s memory access
III. It is beneficially employed for I/O devices with shorter bursts of data transfer
Which of the above statements are advantages of cycle stealing in DMA?

Question 5

When the process is returned after an interrupt service _______ should be loaded again
i) Register Contents
ii) Stack Contents
iii) Condition Codes
iv) Return Address

Question 6

Consider the 4 stage pipeline with the following stages.
Instruction fetch.
Instruction decode.
Execute.
Write back.
The program consists of 16 instructions In which is an unconditional branch instruction transfer the control to In the pipeline, branch target address will be available at the end of execution state. Each instruction spends the same amount of time in all the pipeline stages. The cycle time of the pipeline is 4 ns.
How much time (in ns) is required to execute the above program without using the branch prediction?

Question 7

Assume that the time required for the eight functional units, which operate in each of the eight cycles, are as follows
5ns, 8ns, 6ns, 10ns, 15ns, 12ns, 6ns, 8ns
Assume that pipe lining adds 1ns of overhead. Find the speedup versus the single cycle data path.

Question 8

Assume that the control memory is 24 bits wide. The control portion of the microinstruction format is divided into two fields. A micro-operation field of 13 bits specifies the micro-operations to be performed. An address selection field specifies a condition, based on the flags that will cause a microinstruction branch. There are eight flags.
a) How many bits are in the address selection field?
b) How many bits are in the address field?
c) What is the size of the control memory?
What is the answer to the above questions?

Question 9

A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers and it needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________

Question 10

Find how much disk space (in surfaces) will be required to store 300,000 120-byte logical records, if the disk is fixed sector with 512 bytes/sector, with 96 sectors/track, 110 tracks per surface, and 8 usable surfaces. Ignore any file header records and track indices and assume that records cannot span two sectors.

Question 11

In designing a computer’s cache system, the cache block (or cache line) size is an important Parameter. Which one of the following statements is correct in this context?

Question 12

A hard disk has 500 cylinders, 5 platters, and each platter has 2 surfaces and 128 tracks. Each track has 128 sectors. The sector address is represented by <cyl, sur, sector> where cyl is cylinder number, sur is surface number, and the sector is sector number of the hard disk. Sector 0 address is <0, 0, 0>, Sector 1 address is <0, 0, 1>. What is the cylinder number for the

sector?