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DFCCIL EE/EC EDC QUIZ - 4

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Question 1

Which of the following is true?

Question 2

In Avalanche photo diode assume the saturation velocity of the charge carriers generated by impact ionization by photon absorbtion be equal to 107 cm/sec in a depletion region that is 10Description: E:\Gate\Gate-EC\03_Elctro-Devic_B-done_files\image002.pngm wider then the transition time will be

Question 3

If P is Passivation, Q is n–well implant, R is metallization and S is source/drain diffusion, then the order in which they are carried out in a standard n–well CMOS fabrication process, is

Question 4

Match List – 1 (Fabrication step in IC) with List – 2 (Related characteristic/Reason) and select the correct answer using the codes given below the lists:

Question 5

For the circuit shown below, the minimum number and the maximum number of isolation regions are respectively

Question 6

Photomasking process in IC fabrication:
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Jul 2ESE & GATE EC

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V V Satya Narayana MadasuV V Satya Narayana MadasuMember since Sep 2020
Gate Qualified in 2018,2019,2020,2021| ISRO Exam qualified| AIR -672|Completed M.Tech in VLSI Design
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