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DFCCIL EE/EC EDC QUIZ - 4
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Question 1
Which of the following is true?
Question 2
In Avalanche photo diode assume the saturation velocity of the charge carriers generated by impact ionization by photon absorbtion be equal to 107 cm/sec in a depletion region that is 10
m wider then the transition time will be
![Description: E:\Gate\Gate-EC\03_Elctro-Devic_B-done_files\image002.png](https://gradeup-question-images.grdp.co/liveData/PROJ1513/1481093936168467.png)
Question 3
If P is Passivation, Q is n–well implant, R is metallization and S is source/drain diffusion, then the order in which they are carried out in a standard n–well CMOS fabrication process, is
Question 4
Match List – 1 (Fabrication step in IC) with List – 2 (Related characteristic/Reason) and select the correct answer using the codes given below the lists:
![](https://gradeup-question-images.grdp.co/liveData/PROJ20164/1534140196971530.png)
![](https://gradeup-question-images.grdp.co/liveData/PROJ20164/1534140196971530.png)
Question 5
For the circuit shown below, the minimum number and the maximum number of isolation regions are respectively
![](https://gs-post-images.grdp.co/2018/8/01-img1534141577761-20.TIF)
![](https://gs-post-images.grdp.co/2018/8/03-img1534141742465-46.jpg-rs-high-webp.jpg)
![](https://gs-post-images.grdp.co/2018/8/03-img1534141742465-46.jpg-rs-high-webp.jpg)
Question 6
Photomasking process in IC fabrication:
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Jul 2ESE & GATE EC