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Computer Organisation & Architecture : Nuclear Quiz 2

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Question 1

Consider the two micro-programs:
S1: T1: Acc→ MBR ; Acc_out, MBR_in
T2: IR [Address]→ MAR; IR[Address]_out, MAR_in
T3: Mem [MAR]← MBR; MAR_out, MBR_in
S2: T1: IR [Address]→ MAR; IR[Address]_out, MAR_in
T2: Acc→ MBR ;Acc_out, MBR_in
T3: Mem [MAR]← MBR ; MAR_out, MBR_in
Which of the following Micro-Program works correctly for the Operand store using direct addressing mode?

Question 2

Identify the true statement from the given statements. Program relocation at run time:

1. requires transfer complete block to some memory locations.

2. requires both base address and relative address.

3. requires only absolute address.

Question 3

RISC proccessor has which of the following control unit?

Question 4

Horizontal micro-instructions have which of the following attributes?
1) Short formats
2) Limited ability to express parallel micro-operations
3) Considerable encoding of the control information

Question 5

Which of the following is not true about RISC?

Question 6

Given below are two statements:

Statement I: Hardwired control unit can be optimized to produce fast mode of operation.

Statement II: Indirect addressing mode needs two memory reference to fetch the operand.
From above statements. choose the correct answer from the options given below

Question 7

Consider a non-pipelined machine with 6 stages; the lengths of each stage are 20ns, 10ns, 30ns, 25ns, 40ns, and 15ns, respectively. For implementing the pipelining, the machine adds 5ns of overhead to each stage for clock skew and set up. What is the speed-up factor of the pipelining system (ignoring any hazard impact)?

Question 8

To increase the speed of memory access in pipelining, we make use of _______

Question 9

Which hazard occurs when instruction J tries to write data before instruction, I reads it.

Question 10

ALU operations are performed in which stage of the pipeline?

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GATE & PSU CS Computer Organization and Architecture

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