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# GATE CS 2021 : Digital Logic 8

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Question 1

A twisted ring counter is implemented using 4 D-flip flops. If each FF has 40nsec of delay, what is the maximum usable clock frequency which ensures that there are no timing violations?

Question 2

Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is

Question 3

What is the value of A*B+C for a MOD-24 counter where A is the number of flip flop for ripple counter, B is the number of flip flop of ring counter, C is the number of the flip flop of johnson counter (used for the above given MOD value)?

Question 4

Let the two counter be modulus-7 & modulus-3 counter and both are cascaded with 7MHz clock frequency applied on it, then what is the lowest frequency in KHz?

Question 5

If the connection of the input 3X8 decoder is as shown in the figure, then the output F(A,B,C) can be expressed as -

Question 6

Consider the given circuit,

In this circuit, the race around

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Sep 16GATE & PSU CS

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