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GATE CS 2021 : Computer organization 5 (App update required to attempt this test)

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Question 1

Consider the following statements:

(i) Execution time for single instruction on six stage pipelined CPU is less than or equal to identical non-pipelined CPU.
(ii) In a uniform delay pipeline execution time is equal to the execution time of non-pipelined.

Question 2

Consider a 4-stage pipelined CPU from S1 o S4, we want to execute the program with five instruction (I1 to I5) shown below with the respective number of clocks required in the segments.

Total number of clocks required for the above program is _______ .

Question 3

The concept of pipelining improves performance by

Question 4

Consider the two processors P1 and P2 with intermediate register gateway is 0.

P1 : Has four stage pipeline with stage latency 1.5 nsec, 2 nsec, 1 nsec and 0.5 nsec.
P2 : Has five stage pipeline with stage latency 1 nsec, 2.5 nsec, 1.5 nsec, 2 nsec and 1 nsec.

If each processor has infinite number of instruction to execute, then which of the following is true?

Question 5

Considering two pipeline A and B. where pipeline A is having 8 stages of uniform delay of 1.2ns.

Pipeline B is having 5 stages with a delay of 3ns,6 ns ,7n,4ns,2ns.

How much time is saved when 200 tasks is pipelined using A instead of B write the nearest integer?

Question 6

Consider a 4- Stage pipeline with respective stage delays of 20ns, 30ns, 40ns & 60ns. Interface register is used between the stages which is having delay of 5ns.What is the performance gain when very large no of instructions are executed _______?
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Oct 24GATE & PSU CS

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Priya UpadhyayPriya UpadhyayMember since Sep 2020
Priya Upadhyay
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