GATE CS 2021 : Computer organization 5 (App update required to attempt this test)

Consider the following statements:

(i) Execution time for single instruction on six stage pipelined CPU is less than or equal to identical non-pipelined CPU.
(ii) In a uniform delay pipeline execution time is equal to the execution time of non-pipelined.

Consider a 4-stage pipelined CPU from S₁ o S₄, we want to execute the program with five instruction (I₁ to I₅) shown below with the respective number of clocks required in the segments.

Total number of clocks required for the above program is _______ .

The concept of pipelining improves performance by?

Consider the two processors P₁ and P₂ with intermediate register delay is 0(negligible).

P₁ : Has four stage pipeline with stage latency 1.5 nsec, 2 nsec, 1 nsec and 0.5 nsec.
P₂ : Has five stage pipeline with stage latency 1 nsec, 2.5 nsec, 1.5 nsec, 2 nsec and 1 nsec.

If each processor has infinite number of instruction to execute, then which of the following is true?

Considering two pipeline A and B. where pipeline A is having 8 stages of uniform delay of 1.2ns.

Pipeline B is having 5 stages with a delay of 3ns,6 ns ,7n,4ns,2ns.

How much time is saved when 200 tasks is pipelined using A instead of B write the nearest integer?

Consider a 4- Stage pipeline with respective stage delays of 20ns, 30ns, 40ns & 60ns. Interface register is used between the stages which is having delay of 5ns.What is the performance gain when very large no of instructions are executed _______?