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GATE CS 2021: COA Rapid Mini Mock (App update required to attempt this test)

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Question 1

Which register of current procedure resemble physically similar to the parameter register of called procedure during register to register operation in an overlapping window of RISC Processors?

Question 2

Consider a hypothetical CPU, which supports 46 register window, 16 global registers, 24 local registers 16 IN register and 16 OUT registers. What is the difference between window size and register file size_________________.

Question 3

Consider a 2ns non pipelined processor which consumes 8 cycle for LOAD instruction, 6 cycle for ALU instruction and 2 cycle for branch instruction. Relative frequencies of these instructions are (60%, 20%, 20%) respectively. It is tried to enhance the processor, and pipeline is introduced in the system. In this process, 0.8 ns clock overhead is added to the cycle time. The performance gain after enhancement of the system is ____________________.

Question 4

A Program runs for 200 seconds on a uniprocessor. 10% of the program can be parallelized on a

Multiprocessor (F = 0.2). Assume a multiprocessor with 20 processors.

Compute the speedup.

Question 5

A pipelined processor uses 5 stages with execution time of 3,4,3,2,4 cycles respectively. The corresponding non-pipelined processor uses 8 clock cycles to complete a instruction (ignore buffer delay). Calculate speedup assuming that a very large number of instruction are to be executed.

Question 6

Consider a hypothetical processor operating on 500 MHZ frequency which uses different operand accessing modes described below:

Consider the following data regarding different operations performed:

The average operand fetch rate of CPU is____________________ MIPS.

Question 7

Consider the 32-bit hypothetical process which support 1-word long instruction placed in a 32 KB memory space. Instruction contain 2 register operand ,1-immediate operand.

Process contain instruction set size of 400.Processor support 64 register with 32 bit long. What is the largest unsigned constant possible in the instruction?

Question 8

If following instruction is executed on a system having big endian mechanism implemented.

mov AX, [2000]

where AX is destination register of 16 bits, and memory locations [1999], [2000] and [2001] contain 20, 24 and 12 respectively. What does the AX register contain at the end of this instruction?

Question 9

Consider a processor that includes a base register with indexing addressing mode. Suppose an instruction is encountered that employs this addressing mode and specifies a displacement of 7B2, in hexadecimal. Currently the base and index register contain the decimal numbers 48022 and 8, respectively. What is the address of the operand (In Decimal)?

Question 10

Define the following for a disk system: Let ts asseek time; average time to position head over track. ‘r’ be rotation speed of the disk, in revolutions per second. ‘n’ be number of bits per sector. ‘N’ be capacity of a track, in bits. Tatime to access a sector.
Which of the following is correct?

Question 11

Consider a magnetic disk drive with 8 surfaces, 512 tracks per surface, and 64 sectors per track. Sector size is 1 KB. The average seek time is 8 ms, the track-to-track access time is 1.5 ms, and the drive rotates at 3600 rpm. Successive tracks in a cylinder can be read without head movement.
What is the average access time for a 5 MB file and burst transfer rate? Assume this file is stored in successive sectors and tracks of successive cylinders, starting at sector 0, track 0, of cylinder i.

Question 12

Consider a system having 60% of its instruction is write operations. Hit rate for read operation is 0.7. Cache access time and main memory access time is 3 ns and 75 ns respectively. Then average access time of the system in ns if write through policy is used.
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Dec 4GATE & PSU CS

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Harshita AgarwalHarshita AgarwalMember since Jul 2020
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