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GATE 2020: Digital Electronics Quiz 4 (App update required to attempt this test)
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Question 1
The frequency at the output of the following cascaded circuit is …………. Hz.
Question 2
The sequence generated by the following sequential circuit is
Question 3
The divide by N counter is shown below. If initially Q0 = 0, Q1 = 1, Q2 = 0 the value of N is _______.
Question 4
Which one of the following statements is true about the digital circuit shown in the figure?
Question 5
Assuming that all flip flop are in reset condition initially, the count sequence at Q2 in the circuit shown is
Question 6
The initial state of the digital circuit given below is ‘01’
The state of circuit after 7 clock pulses is ____.
The state of circuit after 7 clock pulses is ____.
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Jul 3ESE & GATE EE