BARC 2020: Mini Mock 4 (App update required to attempt this test)
Attempt now to get your rank among 247 students!
Calculate following an unpipelined processor has a cycle time of 25ns, what is the cycle time of a pipelined version of the processor with 5 evenly divided pipeline stage, if each pipeline latch has latency of 1ns?
Which of the following statements is false regarding to instruction pipelining?
In case of direct mapping of cache, the mapping is expressed as _______
Assume there are 47 different opcodes, 32-registers in the machine. Every instruction has 2 registers as input and 1 register as output [opcode R1, R2, R3]. Find the number of bits to encode an instruction?
Which of the following is used to generate hardware interrupt?
The time delay to check whether an Element is present in cache or not is called
ALU, bus and all registers are identical in size. The instruction ‘Memory write’ has the register transfer interpretation. Find the minimum number of clock cycles needed for execution of the following instruction.
Which of the following is false about CISC architectures?
Consider 4-block cache (initially empty) with the following main memory block references. 4, 5, 7, 12, 4, 5, 13, 4, 5, 7 Identify the hit ratio for Direct mapped cache?
If instruction length in a system is 32 bits and memory has 32 words. Then find the 1 address instructions if there are 42 address instructions’.
The decimal number -39 is expressed in 2’s complement form as
A + A’B + A’B’C + A’B’C’D + ......=
Consider the circuit given below Which of the following statements is true for Y.
The output of the circuit shown in the following figure is equal to
The output Y in the circuit below is always ‘1’ when
Consider the following min term expression for F: The min terms 2, 7, 8 and 13 are ‘do not care’ terms. The minimal sum-of-products form for F is
The logic realized by the circuit shown in figure is.
Match the following –
With 3 Boolean variables, how many Boolean expressions can be formed.
Which of the following is correct regarding asynchronous sequential counters?