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BARC 2020: Mini Mock 4 (App update required to attempt this test)

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Question 1

Calculate following an unpipelined processor has a cycle time of 25ns, what is the cycle time of a pipelined version of the processor with 5 evenly divided pipeline stage, if each pipeline latch has latency of 1ns?

Question 2

Which of the following statements is false regarding to instruction pipelining?

Question 3

In case of direct mapping of cache, the mapping is expressed as _______

Question 4

Assume there are 47 different opcodes, 32-registers in the machine. Every instruction has 2 registers as input and 1 register as output [opcode R1, R2, R3]. Find the number of bits to encode an instruction?

Question 5

Which of the following is used to generate hardware interrupt?

Question 6

The time delay to check whether an Element is present in cache or not is called

Question 7

ALU, bus and all registers are identical in size. The instruction ‘Memory write’ has the register transfer interpretation. Find the minimum number of clock cycles needed for execution of the following instruction.

Question 8

Which of the following is false about CISC architectures?

Question 9

Consider 4-block cache (initially empty) with the following main memory block references.
4, 5, 7, 12, 4, 5, 13, 4, 5, 7
Identify the hit ratio for Direct mapped cache?

Question 10

If instruction length in a system is 32 bits and memory has 32 words. Then find the 1 address instructions if there are 42 address instructions’.